Process for fabricating small size electrodes in an integrated c

Details Process for fabricating small size electrodes in an integrated c Process for fabricating small size electrodes in an integrated c

1989-12-12

1990-11-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437189, 437191, 437200, 437 41, H01L 21469, H01L 2144, H01L 2148

Patent

active

049686461

ABSTRACT:
According to the invention, a first layer of conductive material (11) is submitted to an incomplete etching operation in the presence of a mask (13). After elimination of the mask, a second layer of conductive material is deposited, and the thus-obtained result is submitted to an etching operation without a mask, so allowing the inter-electrode gaps to be reduced.
The process provides a very tight electrode configuration, and is particularly suited to charge-coupled devices.

REFERENCES:
patent: 4727038 (1988-02-01), Watabe et al.
patent: 4818715 (1989-04-01), Chao
patent: 4837180 (1989-06-01), Chao
patent: 4849069 (1989-07-01), Evans et al.
patent: 4863879 (1989-09-01), Kwok
Journal of the Electrochemical Society, vol. 130, No. 9, Sep. 1983, pp. 1894-1897, Manchester, N.H., U.S.; R. M. Levin, et al.: "Oxide Isolation for Double-Polysilicon VLSI Devices".

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