Etching a substrate: processes – Nongaseous phase etching of substrate – Using film of etchant between a stationary surface and a...
Reexamination Certificate
1999-07-14
2002-01-15
Gulakowski, Randy (Department: 1746)
Etching a substrate: processes
Nongaseous phase etching of substrate
Using film of etchant between a stationary surface and a...
C216S088000, C216S067000, C438S471000, C438S691000, C438S692000
Reexamination Certificate
active
06338805
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process for fabricating semiconductor wafers. More specifically, the present invention relates to a simplified process for fabricating semiconductor wafers wherein modified double side polishing is used in combination with plasma assisted chemical etching to create a flat semiconductor wafer capable of extrinsically gettering and removing impurities from both the finished front surface of the wafer and the wafer bulk to the back surface during processing and device manufacturing.
Semiconductor devices are generally fabricated on a silicon semiconductor wafer which has been sliced from a single crystal silicon ingot grown by the so-called Czochralski method. In this process, polycrystalline silicon (“polysilicon”) is charged to a crucible, the polysilicon is melted, a seed crystal is immersed into the molten silicon and a single crystal silicon ingot is grown by slow extraction.
As illustrated in
FIG. 1
, after the wafers are sliced (A) from the monocrystalline ingot, the wafers are conventionally treated with a number of processing steps to produce “finished” silicon wafers having a mirror-like front surface ready for device manufacturing. These steps include etching (B) and cleaning (C) the sliced wafer to remove contaminants and debris produced during the slicing operation (A), lapping/grinding (E) the front surface, cleaning (F) and etching (G) the front surface, and polishing the front surface with a pre-polish (H) and a final touch polish (I) prior to a final cleaning step (J) to produce a finished wafer. Additional flattening steps are also generally employed to decrease total thickness variation, or “TTV,” which is frequently used to measure global flatness variation, which is the difference between the minimum and maximum wafer thickness. Flatter wafers are generally more desirable for device manufacturing. Also, an optional laser marking step (D) may be employed early in the process for wafer identification. In order to getter unwanted impurities and contaminants such as transition or heavy metals from the bulk and front surface regions of the wafer to improve various properties of the wafer, a separate external gettering step (K) is required during wafer processing. This gettering step is generally performed prior to final touch polishing to eliminate contamination of the finished front surface of the wafer.
Although several methods are available to create external gettering of the wafer, the most common include processes such as polysilicon coating or sandblasting to form a deformation layer on the back surface of the wafer to attract impurities away from the front surface and bulk region of the wafer. Recently, external gettering of the wafer has been created by diffusing phosphorous into the back surface of the wafer. These methods each require a separate processing step which increases the complexity and cost of the manufacturing process. Additionally, polysilicon coating or phosphorous diffusion may lead to contamination of the front surface of the wafer during processing, and thus may require the use of “masking” layers to increase effectiveness. This further adds to the time and cost of producing wafers having external gettering. As such, a need exists in the semiconductor industry for a low cost, improved method of processing semiconductor wafers having external gettering.
SUMMARY OF THE INVENTION
Among the objects of the present invention, therefore, are the provision of an improved process for manufacturing semiconductor wafers; the provision of a process for manufacturing semiconductor wafers having external gettering created without additional processing steps; the provision of a process for manufacturing extremely flat semiconductor wafers; the provision of a semiconductor manufacturing process which produces wafers with a decreased number of defects; and the provision of a semiconductor manufacturing process which eliminates the need for grinding/lapping operations.
Briefly, therefore, the present invention is directed to a process for fabricating a semiconductor wafer with extrinsic gettering. The process comprises first subjecting both the front and back surfaces of the wafer to a double side polishing operation to remove material from both surface and create damage on both surfaces. Next, the front surface of the wafer is subjected to a plasma assisted chemical etching operation to flatten the wafer and remove damage from the front surface caused by the double side polishing operation. Finally, the front surface of the wafer is subjected to a touch polishing operation to prepare the wafer for further device manufacturing.
The invention is farther directed to a process for fabricating a semiconductor wafer with extrinsic gettering. The process comprises first slicing the wafer from a silicon ingot and etching the wafer to remove slicing residue. Next, both the front and back surfaces of the wafer are subjected to a double side polishing operation to remove material and create damage on both surfaces. After a cleaning operation, the front surface of the wafer is subjected to a plasma assisted chemical etching operation to flatten the wafer and remove damage from the front surface. Finally, the wafer is rinsed, polished, and cleaned to produce a finished wafer.
Other objects and features of this invention will be in part apparent and in part pointed out hereinafter.
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Seimitsu Kikai, Double Side Polishing for VLSI of Silicon Wafer—One Side Mirror Polishing Considered with Etched Wafer Roughness; Journal of the Japan Society of Precision Engineering, vol. 59, No. 7, pp. 1163-1168.
PCT International Application No. PCT/US 00/18965 Search Report, filing date Jul. 12, 2000.
Ahmed Shamim
Gulakowski Randy
MEMC Electronic Materials , Inc.
Senniger Powers Leavitt & Roedel
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