Process for fabricating semiconductor devices with self-aligned

Details Process for fabricating semiconductor devices with self-aligned Process for fabricating semiconductor devices with self-aligned

1990-11-09

1992-04-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437 33, 437984, 148DIG11, H01L 2128

Patent

active

051067838

ABSTRACT:
A novel process is disclosed for fabricating semiconductor devices with self-aligned contacts. Characteristic of the resulting structure is a digitated electrode and a contiguous conductive region that contact first semiconductor regions and second semiconductor regions, respectively. The first semiconductor regions and the second semiconductor regions are formed in a semiconductor substrate, with each second semiconductor region underlying a finger of the digitated electrode. Advantageously, by forming a contiguous conductive region over the first semiconductor regions located between the fingers of the digitated electrode, it is not only possible to contact second semiconductor regions with a common electrode, but also to self-align the common electrode with the digitated electrode. Ohmic shorting between the digitated electrode and the contiguous conductive region is prevented by interposing an insulating region therebetween. Furthermore, with a single common electrode contacting the second semiconductor regions, it is possible, among other things, to effectively reduce the parasitic capacitances of the semiconductor device as well as achieve dimensional scaling since ohmic contact to the conductive region can be made outside the fingers where physical dimensions are of no limitation.

REFERENCES:
patent: 4707456 (1987-11-01), Thomas et al.
patent: 4871684 (1989-10-01), Glang et al.
patent: 4980304 (1990-12-01), Chin et al.

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