Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-07-26
2001-11-20
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S254000, C438S397000, C438S398000, C438S745000, 43, 43, 43
Reexamination Certificate
active
06319790
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a fabrication technology for a semiconductor device and, more particularly, to a process for fabricating a semiconductor device with a multiple cylindrical capacitor.
DESCRIPTION OF THE RELATED ART
A dynamic random access memory is a typical example of the semi-conductor device. Dynamic random access memory cells are integrated on a semiconductor chip together with peripheral circuits. A popular circuit configuration of the dynamic random access memory cell is implemented by a series combination of an access transistor and a storage capacitor. The circuit configuration is so simple that the dynamic random access memory achieves large data storage density. However, a problem is encountered in the dynamic random access memory cell. When the dynamic random access memory cell is scaled down, the capacitance is too small to hold a data bit in the storage capacitor over a refreshing cycle. In order to increase the capacitance without sacrifice of the occupation area, various three-dimensional structures have been proposed.
The three-dimensional storage capacitors are categorized into two groups. The first group is called as “stacked capacitor”, and the second group is “trench capacitor”. There is a trade-off between the stacked capacitor and the trench capacitor. The stacked capacitor is superior to the trench capacitor in resistance against alpha-particles and noise from the peripheral circuits. This feature is attractive, because, even if the stacked capacitor is not large in capacitance, the data holding characteristics are stable. For this reason, the manufacturers think it appropriate to employ the stacked capacitors in 4-Gbit semiconductor random access memory devices designed under 0.13 micron rules for the next generation.
A storage capacitor with a cylindrical storage node is classified in the stacked capacitor. The storage capacitor with a cylindrical storage electrode is hereinbelow referred to as “cylindrical stacked capacitor”. Typical examples of the cylindrical stacked capacitor are disclosed in Japanese Patent Publication of Unexamined Application (laid-open) Nos. 9-129845 and 9-219499. The prior art cylindrical stacked capacitor has a multiple cylindrical structure so as to increase the surface area of the storage electrode.
The prior art cylindrical storage capacitor is fabricated as shown in
FIGS. 1A
to
1
C. The process starts with preparation of a silicon substrate
101
. Dopant impurity is introduced into a surface portion of the silicon substrate
101
, and is opposite in conductivity type to that of the silicon substrate
101
. An inter-layered insulating layer
103
is deposited over the entire surface of the silicon substrate
101
, and the impurity region
102
is covered with the inter-layered insulating layer
103
. A node contact hole is formed in the inter-layered insulating layer
103
by using a photo-lithography and an etching technique, and the impurity region
102
is exposed to the node contact hole. Phosphorous-doped polysilicon is deposited over the entire surface of the resultant structure. The node contact hole is filled with the phosphorous-doped polysilicon, and the phosphorous-doped polysilicon forms a layer on the inter-layered insulating layer
103
. The phosphorous-doped polysilicon layer is removed from the resultant structure. There remains a contact plug
105
of the phosphorous-doped polysilicon in the node contact hole.
Subsequently, insulating material is deposited over the inter-layered insulating layer
103
, and the contact plug
105
is covered with the insulating layer
106
. A groove is formed in the insulating layer
106
by using the photo-lithography and an etching technique, and the contact plug
104
is exposed to the groove. Conductive material is deposited over the entire surface of the resultant structure, and a conductive layer
108
is conformably formed on the entire surface. The inner surfaces, which define the groove, are covered with the conductive layer
108
. Insulating material such as silicon oxide is deposited over the entire surface of the resultant structure, and the silicon oxide layer is conformably laminated on the conductive layer
108
. The resultant structure is subjected to an etch-back, and the silicon oxide layer is anisotropically etched until the conductive layer
108
is exposed, again. A reactive ion etching technique is used as the anisotropic etching. Then, there remains a side wall spacer
109
on the vertical portions of the conductive layer
108
as shown in FIG.
1
A.
Subsequently, conductive material is deposited over the entire surface of the resultant structure, and a conductive layer
110
is conformably formed on the entire surface of the resultant structure. The side wall spacer
109
is sandwiched between the inner conductive layer
108
and the outer conductive layer
110
(see FIG.
1
B). However, the horizontal portions of the conductive layer
108
are directly laminated with the conductive layer
110
.
The resultant structure is subjected to the etch-back, and the conductive layers
108
/
110
are anisotropically etched away. There remain the conductive layers
108
/
110
on the vertical inner surfaces and the bottom surface defining the groove. Thus, an outer conductive cylinder
111
and an inner conductive cylinder
112
are formed from the conductive layers
108
and
110
, respectively, as shown in FIG.
1
C.
The side wall spacer
109
is selectively etched away, and the outer conductive cylinder
111
and the inner conductive cylinder
112
are left in the groove. The outer conductive cylinder
111
and the inner conductive cylinder
112
are electrically connected through the conductive plug
105
to the impurity region
102
, and serve as a cylindrical storage electrode of a storage capacitor.
The prior art cylindrical storage electrode has the double cylindrical structure, and the side wall spacer
109
is indispensable for the separation deposition of insulating material and the etch-back are required for the side wall spacer
109
. A problem is encountered in the prior art fabrication process in the applicability to the next generation. In detail, a semiconductor dynamic random access memory device of the next generation is to have a cylindrical stacked electrode with more than two conductive cylinders. Accordingly, more than one side wall spacer is required for the cylindrical stacked electrode. If the prior art fabrication process is applied to the cylindrical stacked electrode, the deposition of silicon oxide and the etch-back are repeated more than once. The side wall spacers would make the fabrication process complicated, and the production cost is increased. This results that the semiconductor dynamic random access memory device of the next generation is so expensive. Thus, the prior art fabrication process is not appropriate to the semiconductor dynamic random access memory device of the next generation.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a process for fabricating a semiconductor device which is simple and economical.
To accomplish the object, the present invention proposes to simultaneously form a multiple cylindrical electrode after deposition of conductive layers alternated with mask layers.
In accordance with one aspect of the present invention, there is provided a process for fabricating a semiconductor integrated circuit device comprising the steps of a) forming a groove in a first insulating layer over a semiconductor substrate, b) conformably forming, a conductive layer and a mask layer on an upper surface of the first insulating layer and an inner surface defining, the groove, c) repeating the step b) so that plural conductive layers and the plural mask layers form in combination a lamination conformably extending on the upper surface and the inner surface, d) anisotropically etching the lamination so as to form a multiple cylindrical structure in the groove, c) completing a multiple cylindrical electrode on the basis of the multiple c
Elms Richard
Luu Pho
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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