Process for fabricating semiconductor components

Fishing – trapping – and vermin destroying

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148DIG43, 148DIG50, 1566591, 156660, 1566611, 357 55, 357 58, 437203, H01L 21265, B01J 1700

Patent

active

046929983

ABSTRACT:
A process for the fabrication of semiconductor components and in particular a process in which the components are fabricated with a controlled spacing of etched channels. The process is in particular utilized in fabricating a monolithic array of elements such as a pin diode array. The process of the present invention combines the use of an anisotropic silicon etching process for the desired device geometries with a means of defining all device surface topology by substantially a single photomask thus eliminating critical mask alignment. A second embodiment of the invention is also described employing fewer layers of deposition with a double photomask step.

REFERENCES:
patent: 4004341 (1977-01-01), Tung
patent: 4083098 (1978-04-01), Nicholas
patent: 4243997 (1981-01-01), Natori et al.
In Re Garrett Corp. vs. United States, 164 USPQ 521.
Ex Parte Goell and Smith, 212 USPQ 384.

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