Process for fabricating self-aligned silicide lightly doped drai

Fishing – trapping – and vermin destroying

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437200, 437202, 437 41, 437931, 156643, 156653, 357 233, 148DIG147, 148DIG105, H01L 21265, H01L 2144, H01L 2148

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active

048552470

ABSTRACT:
In a method for fabricating an MOS structure, in accordance with one embodiment, a layer of material that serves as an etching stop during the side wall spacer etch, is inserted between the silicon substrate and the side wall spacer. In another embodiment of the invention, after establishing differential layer thicknesses on the source/drain surface, the side wall spacer is completely removed and light and heavy ion implantation steps are performed sequentially with one single lithographic step. In a further embodiment of the invention, after the self-aligned silicide is formed, the side wall spacer is removed, and light and heavy ion implantation steps are sequentially performed.

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Wang, "Lithographically Defined Self-Aligned Double-Implanted Doped FET Device", IBM Technical Disclosure Bulletin, vol. 27, No. 8, Jan. 1985, pp. 4629-4631.

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