Process for fabricating self-aligned silicide lightly doped drai

Details Process for fabricating self-aligned silicide lightly doped drai Process for fabricating self-aligned silicide lightly doped drai

1988-12-29

1990-03-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 28, 437 41, 437931, 357 233, 156643, 156653, H01L 21265

Patent

active

049083260

ABSTRACT:
In a method for fabricating an MOS structure, in accordance with one embodiment, a layer of material that serves as an etching stop during the side wall spacer etch, is inserted between the silicon substrate and the side wall spacer. In another embodiment of the invention, after establishing differential layer thicknesses on the source/drain surface, the side wall spacer is completely removed and light and heavy ion implantation steps are performed sequentially with one single lithographic step. In a further embodiment of the invention, after the self-aligned silicide is formed, the side wall spacer is removed, and light and heavy ion implantation steps are sequentially performed.

REFERENCES:
patent: 4488351 (1984-12-01), Momose
patent: 4728617 (1988-03-01), Woo et al.
patent: 4740484 (1988-04-01), Norstom et al.
patent: 4818714 (1989-04-01), Haskell
"Process For Making Very Small, Asymmetric, Field-Effect Transistors", IBM Technical Disclosure Bulletin, vol. 30, No. 3, Aug. 1987, pp. 1136-7.
Pfiester, "LDD Mosfet's Using Disposable Sidewall Spacer Technology", IEEE Electron Device Letters, vol. 9, No. 4, Apr. 1988, pp. 189-192.
Ghandhi, VLST Fabrication Principles, John Wiley and Sons, Inc., 1983, pp. 353-354.
Wolf et al., Silicon Processing For the VLSI Era, Vol. 1: Process Technology, Lattice Press, 1986, pp. 323-325.

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