Process for fabricating sealed semiconductor chip using silicon

Details Process for fabricating sealed semiconductor chip using silicon Process for fabricating sealed semiconductor chip using silicon

1993-01-25

1994-04-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

156648, 437241, H01L 2180

Patent

active

053004612

ABSTRACT:
Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

REFERENCES:
patent: 5024970 (1991-06-01), Mori
T. C. Hall et al., "Photonitride Passivating Coating for IC's", NASA Tech Briefs, vol. 5, No. 2, Summer 1980, pp. 231-232.

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