Process for fabricating reduced-thickness high-resistance load r

Details Process for fabricating reduced-thickness high-resistance load r Process for fabricating reduced-thickness high-resistance load r

1996-07-09

1998-01-06

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 60, 437918, 437968, H01L 218244

Patent

active

057054185

ABSTRACT:
A process for fabricating load resistors for memory cell units of semiconductor SRAM device. The process includes providing a silicon substrate containing an intermediate semiconductor device with a gate structure and source/drain regions for a transistor of the cell unit. A first dielectric layer is then formed over the surface of the silicon substrate, the first dielectric layer having opening vias connecting to the gate electrode of the gate structure and a source/drain region. A polysilicon layer is then deposited. The polysilicon layer is then patterned by etching to form a discontinuity between the gate electrode and one of the source/drain regions. An oxidation resistant layer is formed and patterned for exposing regions of the polysilicon layer designated for the formation of the load resistors. An oxide layer is formed over the surface of the exposed portions of the polysilicon layer, so that the thickness of the designated regions of the polysilicon layer underneath the oxide layer is reduced. These designated regions will form the load resistors. The oxidation resistant layer is then removed. Impurity ions are then implanted into exposed regions of the polysilicon layer, not covered by the oxide layer, which are designated for forming interconnectors for the memory cell unit.

REFERENCES:
patent: 4285117 (1981-08-01), Heeren
patent: 4643777 (1987-02-01), Maeda
patent: 5496762 (1996-03-01), Sandhu et al.
patent: 5514617 (1996-05-01), Liu

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