Fishing – trapping – and vermin destroying
Patent
1996-04-26
1998-04-07
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 12, 437 48, 437240, H01L 218246
Patent
active
057364206
ABSTRACT:
A novel process for fabricating semiconductor devices including read only memory transistor cells. The memory cells are programmed to either a logical one or logical zero state by adjusting the dopant levels in their channel regions, with a programming implantation step being selectively performed on those ones of the memory cell transistors which are to be programmed, with the programming implantation step being performed midway through the fabrication process. By performing this programming step midway through the process, certain advantages are obtained regarding improved turn around time from the receipt of a customer's order, and yet the problems of incomplete activation of implanted dopants and ineffective gettering by the use of low dopant concentration gettering layers is avoided.
REFERENCES:
patent: 3632433 (1972-01-01), Tokuyama
patent: 4294001 (1981-10-01), Kuo
patent: 4342100 (1982-07-01), Kuo
patent: 4358889 (1982-11-01), Dickman et al.
patent: 4359817 (1982-11-01), Dickman et al.
patent: 4364165 (1982-12-01), Dickman et al.
patent: 4364167 (1982-12-01), Dickman et al.
patent: 4365405 (1982-12-01), Dickman et al.
patent: 4513494 (1985-04-01), Batra
patent: 4600933 (1986-07-01), Richman
patent: 4633572 (1987-01-01), Rusch et al.
patent: 4649629 (1987-03-01), Miller et al.
patent: 4828629 (1989-05-01), Ikeda et al.
patent: 4861126 (1989-08-01), Dautartas et al.
patent: 4889820 (1989-12-01), Mori
Wolf, Silicon Processing for the ULSI Era, vol. 1 Lattice Press, pp. 188-189, 1986.
Ghandhi, "VLSI Fabrication Principles" John Wiley & Sons pp. 424-429, 1983.
Research Disclosure #20214, Feb. 1981, "Late programmed SATO ROM fabrication process.
Research Disclosure #20423, Apr. 1981, "Late programming hexagonal cell ROM with double layer polycrystalline silicon fabrication process.
Research Disclosure #20225, Feb. 1981, "Fabrication process for SATO ROM with adjacent SAG IGFETs".
Min Heikyung Chun
Whitney Jeffrey Kent
Chaudhari Chandra
National Semiconductor Corporation
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