Process for fabricating non-volatile field effect semiconductor

Details Process for fabricating non-volatile field effect semiconductor Process for fabricating non-volatile field effect semiconductor

1975-12-30

1977-09-13

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

29571, 29576E, 148187, 148188, 357 23, 357 54, 357 91, H01L 21265, H01L 21324, H01L 2978

Patent

active

040479749

ABSTRACT:
Disclosed is a non-volatile field effect information storage device which can be electrically written and erased. It consists of an insulated gate field effect transistor having a single gate dielectric material formed in two stages. The gate dielectric is made up of two adjacent layers of silicon dioxide, one of which is relatively thin and adjacent to the semiconductor substrate, while the other is relatively thick and implanted with ions at controlled depths and dosages near the interface with the first silicon dioxide layer. With the application of an appropriate control voltage on the gate structure, charges from the adjacent transistor channel region tunnel through the relatively thin layer of silicon dioxide and become stored in the trapping sites introduced by the implanted ions located in the second layer of silicon dioxide and very near the interface between the two silicon dioxide layers. While there, the charges control the conductivity of the channel, and thus the logic state of the transistor.

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Agusta et al., "Metal-Insulator-Trap-Oxide-Semiconductor Memory Cell," I.B.M. Tech. Discl. Bull., vol. 13, No. 12, May 1971, p. 3636.
Double et al., "FET Gate Integrity by Ion Implantation," Ibid., vol. 16, No. 1, June 1973, p. 8.
Burkhardt et al., "Post-Oxidation Annealing - - - Fixed Charged Levels," Ibid., vol. 18, No. 3, Aug. 1975, p. 753.

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