Process for fabricating multiple pillars inside a dram trench fo

Details Process for fabricating multiple pillars inside a dram trench fo Process for fabricating multiple pillars inside a dram trench fo

1992-04-09

1993-04-20

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437228, 437229, 437235, 437919, H01L 2170

Patent

active

052042804

ABSTRACT:
A method is disclosed for fabricating a DRAM trench capacitor with multiple-pillars inside the trench for increased surface area.
A thin pad oxide of a few tens of nonometers is grown on a silicon substrate. A layer of silicon nitride is deposited and another layer of oxide is then deposited. This provides the ONO stack. Then a layer of polysilicon, a layer of nitride, and a layer of large-grained polysilicon are deposited sequentially. Then, a trench is defined by a lithographic mask and the exposed large-grained polysilicon is etched in CF.sub.4. Since CF.sub.4 etches the polysilicon and nitride 20 at almost the same rates, the topographical features existed in the polysilicon layer is copied to the nitride layer. The nitride layer is partially etched. The RIE etching gas is then changed to a mixture of HBR, SiF.sub.4, Helium, and NF.sub.3 which gives a very directional polysilicon etching with a good selectivity to nitride and a very high selectivity to oxide. Consequently, the topographical features on the nitride layer is enhanced and is transferred to the polysilicon layer which is used as a mask to etch the oxide nitride and pad oxide to form pillars.

REFERENCES:
patent: 4803181 (1989-02-01), Buchmann et al.
patent: 5047117 (1991-09-01), Roberts

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