Process for fabricating multilevel metal integrated circuits and

Details Process for fabricating multilevel metal integrated circuits and Process for fabricating multilevel metal integrated circuits and

1986-06-06

1988-11-22

Macon, Robert S.

Fishing, trapping, and vermin destroying

357 65, 357 67, 437 51, 437 56, H01H 2348

Patent

active

047869623

ABSTRACT:
The specification describes a multilevel metal CMOS integrated circuit wherein a first or lower level of metallization comprises strips of tungsten over aluminum. These strips are connected through vias in an inter-metal dielectric layer to an upper or second level of metallization which is photodefined in a desired pattern. The tungsten suppresses hillocks in the underlying aluminum during high temperature processing and also advantageously serves as an etch stop material during integrated circuit fabrication.

REFERENCES:
patent: 4592132 (1986-06-01), Lee et al.
patent: 4651191 (1987-03-01), Ooue et al.

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