Process for fabricating MOS transistor

Fishing – trapping – and vermin destroying

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437 40, 437 45, H01L 21265

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053957806

ABSTRACT:
A process for the fabrication of an MOS transistor.
The process comprises the steps of forming a gate oxide film on a substrate, forming a p.sup.+ polysilicon film doped with p type impurity ions over said gate oxide film, coating an insulating film and a photoresist film over said p.sup.+ polysilicon film, in sequence, subjecting the resultant structure to a patterning to expose a portion of said insulating film, applying an etching method to said exposed insulating film with said photoresist film used as a mask, implanting fluorine ions in said p.sup.+ polysilicon film with resultant insulating film used as a mask, removing the remaining photoresist film, carrying out an annealing method to form a low density p.sup.- source/drain regions, applying an etching method to said p.sup.+ polysilicon film to form a gate with said resultant insulating film used as a mask, removing said resultant insulating film, depositing an oxide film entirely over the resultant structure, applying an anisotropic etching to said oxide film to form spacers at side walls of said gate, implanting p type impurity ions in said substrate at a high density to form high density p.sup.+ source/drain regions neighboring said low density p.sup.- source/drain regions, thereby the device having a storage capacity of not less than 256M can be fabricated more reliably and more advantageously.

REFERENCES:
patent: 4948744 (1990-08-01), Kita
patent: 5082794 (1992-01-01), Pfiester et al.
patent: 5141895 (1992-08-01), Pfiester et al.
patent: 5304504 (1994-04-01), Wei et al.
"Novel Shallow Counter Doping Process and High Performance Buried Channel pMOSFET Using Boron Diffusion Through Oxide" by Y. Toyoshima, et al., Semiconductor Device Engineering Laboratory, Toshiba Corporation; May 1, 1992; pp. 111-112.

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