Process for fabricating monolithic circuits having matched compl

Details Process for fabricating monolithic circuits having matched compl Process for fabricating monolithic circuits having matched compl

1970-09-03

1977-10-18

Wojciechowicz, Edward J.

357 48, 357 34, H01L 2702, H01L 2704, H01L 2972, H01L 736

Patent

active

040548996

ABSTRACT:
A process for fabricating a monolithic integrated circuit having matched semiconductor devices and P-N junction isolation regions, with the collector regions for the semiconductor devices of one polarity type and the isolation regions being formed by up-diffusing impurities from a selected surface of a substrate of one conductivity type though an epitaxial layer of opposite conductivity type formed thereon, so that such collector regions are surrounded by material of opposite conductivity type, and the P-N junction isolation regions selectively isolate semiconductor devices of opposite polarity type from other circuit elements, wherein such collector regions and P-N junction isolation regions have retrograded impurity concentration profiles.

REFERENCES:
patent: 3327182 (1967-06-01), Kisinko
patent: 3465215 (1969-09-01), Bohannon et al.
patent: 3481801 (1969-12-01), Hugle
patent: 3502951 (1970-03-01), Hunts
patent: 3617827 (1970-03-01), Schmitz

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