Process for fabricating low capacitance bipolar junction transis

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 99, 437162, 437 33, 437909, 437968, 437985, 148DIG102, 148DIG117, 148DIG124, H01L 21265

Patent

active

051067676

ABSTRACT:
This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferably polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.

REFERENCES:
patent: 4462847 (1984-07-01), Thompson et al.
patent: 4824799 (1989-04-01), Komatsu
patent: 4851362 (1989-07-01), Suzuki
patent: 4935375 (1990-06-01), Kasper et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process for fabricating low capacitance bipolar junction transis does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating low capacitance bipolar junction transis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating low capacitance bipolar junction transis will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1585669

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.