Process for fabricating lateral PNP transistor structure and BIC

Details Process for fabricating lateral PNP transistor structure and BIC Process for fabricating lateral PNP transistor structure and BIC

1992-09-10

1994-07-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 32, 437 59, 437 26, 437917, 148DIG9, H01L 21265

Patent

active

053267109

ABSTRACT:
A lateral PNP transistor structure is fabricated in a BICMOS process utilizing the same steps as are used during the BICMOS process for fabricating NPN and CMOS transistors without requiring additional steps. A base N+ buried layer B/N+BL formed in the IC substrate P/SUB underlies the bipolar PNP transistor. A base Retro NWELL B/NWELL and a base contact Retro NWELL BC/NWELL are formed in the base N+ buried layer B/N+BL using the CMOS Retro NWELL mask, etch and N type introduction sequence. An epitaxial layer EPI of undoped or low doped EPI is deposited across the IC substrate and isolation oxide regions ISOX isolating the PNP transistor are grown during the isolation oxide ISOX mask, etch and grow sequence. The NPN collector sink definition mask, etch and N type introduction sequence is used to form a PNP base contact N+ sink region BC/N+SINK to the BC/NWELL and B/N+BL. A field oxide spacer FOX is grown during the CMOS active area definition mask, etch and grow sequence for separating the PNP BC/N+SINK from the PNP collector region P+C. A uniform layer of polysilicon POLY is masked and etched during the POLY definition mask and etch sequence to form a self aligned transistor SAT POLY mask for critically defining the PNP base width and base active region. The PNP collector region P+C and emitter region P+E are introduced through the SAT POLY mask using at least one of the NPN base definition mask, etch and P type introduction sequence and PMOS P+S/D mask definition, etch and P type introduction sequence. The PNP base contact region can be formed using the NPN emitter definition mask sequence. The PNP transistor contact surfaces and metal contacts are thereafter prepared according to conventional procedures.

REFERENCES:
patent: 5150177 (1992-09-01), Robinson et al.
patent: 5187109 (1993-02-01), Cook et al.
patent: 5239270 (1993-08-01), Desbiens
patent: 5256582 (1993-10-01), Mosher et al.
patent: 5262345 (1993-11-01), Nasser et al.
patent: 5268312 (1993-12-01), Reuss et al.
patent: 5268316 (1993-12-01), Robinson et al.
patent: 5290718 (1994-03-01), Robinson et al.
Murray J. Robinson, et al. U.S. patent application Ser. No. 655,676, filed Feb. 14, 1991 for Bipolar Transistor Structure and BICMOS IC Fabrication Process.

Affiliated with

Also associated with

Rating

Process for fabricating lateral PNP transistor structure and BIC does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating lateral PNP transistor structure and BIC, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating lateral PNP transistor structure and BIC will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-795729