Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-01-06
2001-10-09
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S297000
Reexamination Certificate
active
06300220
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an isolation structure for semiconductor devices in an integrated circuit, and in particular, to an isolation structure and process providing lateral device isolation utilizing a buried, grown field oxide structure.
2. Description of the Related Art
Semiconductor devices in integrated circuits typically require isolation from adjacent devices in the substrate. For example,
FIG. 1
shows a cross-sectional view of a bipolar transistor isolated from adjacent devices by conventional deep and shallow trench isolation structures.
Conventional PNP bipolar transistor
10
is formed in single crystal silicon
18
featuring subsurface vertical isolation component
32
. Vertical isolation component
32
provides electrical isolation in the vertical direction between buried collector contact region
12
and surrounding single crystal silicon
18
. Vertical isolation component
32
may be formed in a number of ways, including high-energy ion implantation of oxygen into single crystal silicon, followed by oxidation to form vertical isolation component
32
. An alternative way of forming the buried vertical isolation structure is to join oxide surfaces of two separate silicon wafers, and then remove backside silicon of one of the wafers to produce a surface suitable for epitaxial growth. Other methods exist for forming a buried vertical isolation component in addition to those specifically described above.
PNP bipolar transistor
10
also includes buried P-type collector contact region
12
underlying P-type collector
14
. P-type collector sinker structure
16
extends from the surface of single crystal silicon
18
to buried collector contact region
12
. Collector sinker structure
16
is electrically isolated from surrounding bipolar device regions by shallow trench isolation structure
20
.
Conventional PNP bipolar transistor
10
further includes trench isolation structures
34
including deep component
34
a
and shallow component
34
b.
Trench isolation structures
34
provide electrical isolation between buried collector contact region
12
and collector
14
and the surrounding single crystal silicon and any semiconductor devices formed therein.
The base of bipolar transistor
10
includes N-type intrinsic base
22
a
positioned directly underneath P-type emitter
24
, and extrinsic N-type base regions
22
b
adjacent to intrinsic base
22
a.
Electrical contact between extrinsic base
22
b
and the surrounding circuit is made possible through polysilicon base contact
26
. P-type emitter
24
is formed within intrinsic base
22
a,
and polysilicon base contact
26
is separated from the overlying polysilicon emitter contact
28
by dielectric
30
.
While satisfactory for some applications, the conventional trench isolation structure depicted in
FIG. 1
suffers from certain problems. One disadvantage is the difficulty in creating deep trench component
34
a.
The deep trench component can be fabricated in a variety of ways, most of which are complex and give rise to defects. For example, the deep trench component shown in
FIG. 1
can be formed by etching a deep trench within an existing shallow trench, and then filling both the deep and shallow trenches with a dielectric material such as tetraorthosilicate glass (TEOS). Apart from the lithographic challenge of superimposing the deep and shallow trench masks, the high aspect ratio of the deep trench component hinders uniform filling of the deep trench, giving rise to keyhole voids
36
. Formation of keyhole voids
36
can in turn introduce random variation into electronic isolation afforded by the trench isolation structure.
Another conventional approach to fabricating the conventional deep and shallow trench isolation structure is to first form and then fill the deep trench component, followed by creating and filling the shallow component. Unfortunately, this approach requires difficult-to-achieve uniform preferential etching of material outside and inside the already-filled deep trench.
Therefore, there is a need in the art for a process for an easily-formed lateral isolation structure featuring both deep and shallow components which avoids formation of keyhole gaps or other defects.
SUMMARY OF THE INVENTION
The present invention teaches a process flow for forming an isolation structure for a semiconductor device which avoids complex and difficult photolithography steps. Specifically, semiconductor material featuring a subsurface vertical isolation component is removed to create raised precursor active device regions separated by sunken precursor isolation regions. The unmasked sunken precursor isolation regions are then oxidized to grow field oxide structures extending in contact with the subsurface vertical isolation component. The shallow isolation component is created by forming highly conformal dielectric material, such as oxide produced by high density plasma (HDP) techniques, over the resulting surface such that the conformal dielectric penetrates into recesses remaining between the raised active device regions and the grown field oxides.
A first embodiment of a process in accordance with the present invention comprises the steps of providing a semiconductor workpiece including a subsurface vertical isolation component, and patterning an oxidation mask to expose precursor isolation regions. Semiconductor material is then removed from the semiconductor workpiece to form a plurality of raised precursor active device regions separated by a plurality of sunken precursor isolation regions. The semiconductor workpiece is oxidized in the sunken precursor isolation regions to grow dielectric structures extending into the semiconductor workpiece into contact with the subsurface vertical isolation component, such that a plurality of recesses are created between the dielectric structures and the raised precursor active device regions. A dielectric material is formed over the dielectric structures and the raised precursor active device regions, such that the dielectric material penetrates into the recesses. The dielectric material is planarized to stop on the oxidation mask overlying the raised precursor active device regions.
A first embodiment of an isolation structure in accordance with the present invention comprises a vertical isolation component including a layer positioned at a first depth in a semiconductor workpiece, and a lateral isolation component. The lateral isolation component includes a deep lateral isolation component comprising an oxidized structure encompassing an active device region and extending downward into the semiconductor workpiece into contact with the vertical isolation component. The lateral isolation component also includes a shallow lateral isolation component comprising deposited dielectric material extending to a second depth into the semiconductor workpiece more shallow than the first depth.
The features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.
REFERENCES:
patent: 4700454 (1987-10-01), Baerg et al.
patent: 4842675 (1989-06-01), Chapman et al.
patent: 5387539 (1995-02-01), Yang et al.
patent: 5712186 (1998-01-01), Thakur et al.
patent: 5728620 (1998-03-01), Park
patent: 5858842 (1999-01-01), Park
patent: 5872043 (1999-02-01), Chen
patent: 5888881 (1999-03-01), Jeng et al.
patent: 5895253 (1999-04-01), Akram
patent: 6107144 (2000-08-01), Jang et al.
patent: 6159822 (2000-12-01), Yang et al.
patent: 000463510A2 (1992-02-01), None
Yoshida, M., et al. “A Bipolar-Based 0.5 &mgr;m BiCMOS Technology on Bonded SOI for High-Speed LSIs”, IEICE Trans. Electron E77—C (8) :1395-1402 (1994).
Yamaguchi, T., et al., Process Invenstigations for a 30—GHz fT Submicrometer Double Poly-Si BiPolar Technology, IETDAI Transactions on Electron Devices 41(3) :321-239 (1994).
Blum David S.
Bowers Charles
National Semiconductor Corporation
Stallman & Pollock LLP
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