Process for fabricating integrated circuits utilizing ion implan

Details Process for fabricating integrated circuits utilizing ion implan Process for fabricating integrated circuits utilizing ion implan

1974-07-02

1976-01-20

Rutledge, L. DeWayne

Metal treatment

Compositions

Heat treating

357 91, H01L 21265

Patent

active

039335283

ABSTRACT:
A self-aligning process for fabrication of integrated circuits utilizing ion implantation to effect doping. A composed masking technique is used to define self-aligned areas in a silicon oxide layer for definition of isolation, base, resistor and collector contact regions. Only two oxide removal steps are required for isolation through emitter process steps, and the process uses the silicon oxide layer and photoresist material for implantation masking. Formation of the emitter region by ion implantation and by diffusion are described.

REFERENCES:
patent: 3756861 (1973-09-01), Payne et al.
patent: 3793088 (1974-02-01), Eckton, Jr.

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