Process for fabricating integrated circuit structure with extrem

Details Process for fabricating integrated circuit structure with extrem Process for fabricating integrated circuit structure with extrem

1988-01-22

1989-10-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 46, 437 48, 437 49, 437 52, 437 47, 437 60, 437101, 437193, 437228, 437919, 357235, H01L 21263

Patent

active

048747165

ABSTRACT:
A process for obtaining extremely smooth interfaces of poly 1/inter-level dielectric film/poly 2 films. Essentially, the poly 1 layer is LPCVD-deposited in the amorphous phase and implant-doped, after which an appropriate dielectric film is deposited by LPCVD. Following this, the poly 1 is crystallized at a temperature of about 1000.degree. C., after which poly 2 is LPCVD-deposited and POCl.sub.3 -doped at 950.degree. C. The resulting poly 2/inter-level dielectric/poly 1 interfaces are extremely smooth on an atomic scale, even after other device fabrication thermal cycles, and are believed to resutl in superior leakage characteristics.

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Herbeke et al., "LPCUD Polycrystalline Silicon; Growth and Physical Properties of In-Situ Phosphorus Doped and Undoped Films", RCA review, vol. 44, pp. 287-312, Jun. 83.

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