Process for fabricating insulated-gate field-effect transistors

Details Process for fabricating insulated-gate field-effect transistors Process for fabricating insulated-gate field-effect transistors

1977-12-28

1979-04-17

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

148 15, 148187, 156652, H01L 2126

Patent

active

041493079

ABSTRACT:
The specification describes a process for making an insulated-gate field-effect transistor wherein a silicon nitride mask is deposited above the surface of a semiconductor body and is used in one embodiment of the invention in conjunction with a refractory gate member (1) as a mask in the formation of the source and drain regions by the ion implantation of conductivity-type-determining impurities on both sides of the gate and (2) as a mask in the formation of contact holes to the source and drain regions of the transistor for the subsequent provision of metal contacts to these regions. In another embodiment, there is described a process for forming source and drain contacts wherein the mask for the formation of contact holes by oxide etching is also the pattern definition and lift-off mask for the formation of metal contacts to the transistor.

REFERENCES:
patent: 3600218 (1971-08-01), Pennebaker
patent: 3646665 (1972-03-01), Kim
patent: 3681153 (1972-08-01), Clark et al.
patent: 3837907 (1974-09-01), Berglund et al.
patent: 3967981 (1976-07-01), Yamazaki
patent: 3972756 (1976-08-01), Nagase et al.
patent: 4001048 (1977-01-01), Meiling et al.
patent: 4045594 (1977-08-01), Maddocks
patent: 4062707 (1977-12-01), Mochizuki et al.
patent: 4063973 (1977-12-01), Kirita et al.

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