Process for fabricating high performance BiCMOS circuits

Details Process for fabricating high performance BiCMOS circuits Process for fabricating high performance BiCMOS circuits

1989-09-19

1992-01-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 56, 437 59, 437162, 148DIG9, H01L 21265

Patent

active

050791770

ABSTRACT:
A method of making complementary vertical bipolar transistors and complementary field effect transistors on the same substrate is described. The process includes forming buried layers in a semiconductor substrate which are spaced apart in a self-aligned manner by use of a lateral etching technique to undercut the mask used for definition of the buried layers. In the process, the collector and base contacts of the bipolar devices and the corresponding conductivity-type sources and drains of the field effect transistors are combined to minimize processing steps. The process also includes a silicided polycrystalline silicon layer used to form resistors and contact the various transistors.

REFERENCES:
patent: 4764482 (1988-08-01), Hsu
patent: 4797372 (1989-01-01), Verret et al.
Bastani et al., "Advanced One Micron BiCMOS Technology for High Speed 256K SRAM", 1987 VLSI Technology Symposium, Karuizawa, May 18-21, 1987.
Watanabe et al., "High Speed BiCMOS VLSI Technology with Buried Twin Well Structure", IEDM Technical Digest, Washington, D.C., Dec. 1-4, 1985, pp. 423-426.

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