Stock material or miscellaneous articles – Web or sheet containing structurally defined element or... – Composite having voids in a component
Reexamination Certificate
1997-02-13
2001-01-16
Chapman, Mark (Department: 1753)
Stock material or miscellaneous articles
Web or sheet containing structurally defined element or...
Composite having voids in a component
C428S318400, C438S704000, C438S745000
Reexamination Certificate
active
06174596
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture method for semiconductor chips and integrated circuits (ICs). More particularly, this invention relates to a novel and improved method of manufacture by applying a differentiating etching technique on a layer of the semiconductor chip to produce an improved dual damascene structure such that the reliability and performance characteristics of IC devices can be improved by eliminating surface damages caused by deep dry etch and by more precisely control the critical dimensions (CDs) of the interconnect lines and contact plugs.
2. Description of the Prior Art
Several technical difficulties are still faced by those of ordinary skill in the art of the semiconductor manufacture industry in applying a dual damascene process, commonly implemented for deep-sub-micron devices, to form the trenches and the vias in the trenches for interconnect lines and contact plugs to be filled therein respectively. The difficulties are caused by the application of a twice-dry-etch process, which in a second etch process, etching through a dielectric or an oxide layer to make the via for contact plugs. The etched via reaches the top surface of the substrate. This second dry etch process often leads to surface damages to the substrate thus resulting in gate-oxide degradation. Furthermore, due to the nature of the dry etch process, the critical dimensions (CDs) of the vias, formed in the trench for contact plugs, etched by the second etch process, tend to have dimensional variations which are generally more unpredictable and uncontrollable. The greater imprecision of the critical dimensions incurred in the second etch is caused by certain topographical profiles resulted from the first dry etch. Therefore, the reliability and performance characteristics of the devices manufactured by the deep sub-micron technology, applying this conventional dual damascene process, are often adversely affected by these difficulties.
In order to provide a more comprehensive background to better understand the merits of this invention, the fabrication processes commonly employed for a dual damascene structure are illustrated in
FIGS. 1A
to
1
D. Referring to
FIG. 1A
where an oxide layer
15
is supported on a substrate
10
. A plurality of trenches
20
are first formed on the top surface of the oxide layer
15
for the purpose of forming the interconnect lines therein (see
FIG. 1D
below). Only the top portion of the oxide layer
15
is removed in forming the trenches
20
for the interconnect lines. The first dry etch process does not completely penetrate through the oxide layer
20
. Referring to
FIG. 1B
, a photo-resist (not shown) is employed by applying photolithography technique to define the through hole areas. A second dry etch process is then carried out to form the contact plugs through holes
25
in the trenches
20
. As shown in
FIG. 1B
, the through holes
25
penetrate through the oxide layer
20
and reach the top surface of the substrate
10
. A metallization process is then carried out in
FIG. 1C
to form a top metal layer
30
. A planarization process is performed by carrying out a chemical mechanical polishing process (CMP) as shown in
FIG. 1D
to polish and remove the top portion of the metal layer
30
to form the interconnect lines
35
in the trenches
20
and the contact plugs
40
in the through holes
25
. A dual damascene structure is completed as that shown in FIG.
1
D.
During the second dry etch process, the top surface of the substrate
10
is exposed to the etching plasma. As the etch plasma ions continuously penetrate the oxide layer
15
, it is very difficult to control the timing and conditions of the etching plasma during the second dry etch process to assure that the top surface of the substrate
10
will not be over etched or damaged by the etching plasma. Uncontrollable exposure of the top surface of the substrate
10
to the etching plasma during the second etch process in forming the through holes
25
for the contact plugs
40
thus imposes a threat to the quality of the top surface of the substrate
10
and the integrity of the gate oxide layer formed thereon. Problems of device reliability and performance uncertainties may then be resulted from such threats caused by the plasma attacks to the substrate surface.
Additional technical difficulties are caused by the imprecision in controlling the critical dimensions of the through holes
20
formed by the second etch process. As the trenched are formed by a first dry etch process, certain trench profiles are formed at the completion of the first dry etch. The trench profiles resulting from the first dry etch produce certain unknown and uncontrollable dimensional variations. Greater variations in the critical dimensions of the through holes
25
are introduced when applying a second etch to the trenches formed by the first dry etch. The uncertainties in dimensional variations of the through holes
25
formed by the second etch are accumulated and compounded from the variations of the first dry etch and the second etch. Thus, further difficulties in controlling the device reliability and performance characteristics are introduced due to these greater variations in the locations and dimensions of the contact plugs.
Therefore, a need still exists in the art of semiconductor chip and integrated circuit (IC) manufacture to provide a novel manufacture process to resolve the above difficulties. It is desirable that the novel manufacture process to form the dual damascene structure which is simple and easy to implement whereby a lower cost of manufacture can be achieved. Additionally, it is desirable that this novel manufacture process for forming the dual damascene structure provides more control precision in forming the small through holes and trenches for contact plugs and interconnect lines such that semiconductor devices of improved reliability and well controlled performance characteristics can be reliably produced.
SUMMARY OF THE PRESENT INVENTION
It is therefore an object of the present invention to provide a novel and improved manufacture process for forming the dual damascene structure by first applying an etching-rate differentiating technique and a non-damaging etch-through process to an over-layer above the top surface of the semiconductor substrate such that the difficulties and limitations encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a novel and improved manufacture process for performing the task of forming the dual damascene structure by first forming an over-layer with light sensitive materials and applying a non-damaging wet etch to etch through the over-layer through areas first exposed with etch-enhancing light on the over layer thus the damaging effects to the substrate surface may be prevented.
Another object of the present invention is to provide a novel and improved manufacture process for performing the task of forming the dual damascene structure by first forming an over-layer with light sensitive materials and applying a non-damaging wet etch to etch through the over-layer through areas first exposed with etch-enhancing light on the over layer thus whereby the critical dimensions of the through holes provided for contact plugs can be more precisely controlled.
Another object of the present invention is to provide a novel and improved manufacture process for performing the task of forming the dual damascene structure by first forming an over-layer with light sensitive materials and applying a non-damaging wet etch to etch through the over-layer through areas first exposed with etch-enhancing light on the over layer followed by a dry etch to form the trenches for the interconnect lines above the through holes whereby the critical dimensions of both the through holes and the trenches can be more precisely controlled.
Another object of the present invention is to provide a novel and improved manufacture process for performing the task of f
Chapman Mark
Lin Bo-In
Winbond Electronics Corp.
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