Process for fabricating dimensionally stable interconnect boards

Adhesive bonding and miscellaneous chemical manufacture – Methods – Surface bonding and/or assembly therefor

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29829, 29846, 29851, 29852, B32B 3126

Patent

active

046455523

ABSTRACT:
We disclose a process for manufacturing multilayer circuit boards which includes providing a conductive, or an insulating substrate with a conductive pattern thereon, and then transferring and firing a glass-ceramic tape layer to the surface of the substrate. This tape layer provides both electrical isolation between the substrate and electrical conductors or electronic components which are subsequently bonded to or mounted on the top surface of the glass-ceramic tape layer. By providing vertical electrical conductors by means of vias in the tape layer prior to firing the tape layer directly on the substrate, good X and Y lateral dimensionally stability of the tape material is maintained. In addition, a high quality thick film glass-ceramic electrical interconnect structure is achieved at a relatively low manufacturing cost.

REFERENCES:
patent: 3040213 (1962-06-01), Byer et al.
patent: 3371001 (1968-02-01), Ettre
patent: 3423517 (1969-01-01), Arrhenius
patent: 3436819 (1969-04-01), Lunine
patent: 3506473 (1970-04-01), Ettre
patent: 3549784 (1970-12-01), Hargis
patent: 3576668 (1971-04-01), Fenster et al.
patent: 3655496 (1972-04-01), Ettre et al.
patent: 3726002 (1973-04-01), Greenstein et al.
patent: 3728185 (1973-04-01), Gray
patent: 3756891 (1973-09-01), Ryan
patent: 3838204 (1974-09-01), Ahn et al.
patent: 3852877 (1974-12-01), Ahn et al.
patent: 3948706 (1976-04-01), Schmeckenbecher et al.
patent: 3978248 (1976-08-01), Usami
patent: 4030190 (1977-06-01), Varker
patent: 4109377 (1978-08-01), Blazick et al.
patent: 4153491 (1979-05-01), Swiss et al.
patent: 4289719 (1981-09-01), McIntosh et al.
patent: 4299873 (1981-11-01), Ogihara et al.
patent: 4313262 (1982-02-01), Barnes et al.
patent: 4336088 (1982-06-01), Hetherington et al.
patent: 4397800 (1983-08-01), Suzuki et al.
patent: 4406722 (1983-09-01), Chow et al.
patent: 4413061 (1983-11-01), Kumar et al.
patent: 4434134 (1984-02-01), Darrow et al.
patent: 4457950 (1984-07-01), Fujita et al.
patent: 4504339 (1985-03-01), Kamehara et al.

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