Process for fabricating copper interconnects in ultra large scal

Details Process for fabricating copper interconnects in ultra large scal Process for fabricating copper interconnects in ultra large scal

1991-11-12

1994-01-11

Ryan, Patrick J.

Stock material or miscellaneous articles

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428433, 428688, 428209, B32B 900

Patent

active

052779858

ABSTRACT:
The present invention features low-temperature, self-encapsulated, copper interconnect lines on silicon substrates of Ultra-Large Scale Integration (ULSI) circuits. The interconnect lines are a product of a process that includes the following steps: (a) alloying the copper with titanium in an approximate 10 atomic weight percentage of titanium; (b) depositing a layer of the copper/titanium alloy upon a silicon dioxide/silicon substrate of a ULSI circuit; (c) patterning the copper/titanium layer to form interconnect lines on the substrate; (d) forming a titanium rich surface film on the copper interconnect lines by rapid heating of the copper/titanium interconnect lines at an approximate ramping rate of between 60.degree. and 80.degree. C./minute; and (e) nitriding the titanium rich surface of the interconnect lines in an ammonia atmosphere at low temperatures in an approximate range of between 450.degree. to 650.degree. C. for about 15 to 40 minutes, to form a titanium nitride encapsulating layer about said copper interconnect lines.

REFERENCES:
patent: 4151325 (1979-04-01), Welch
patent: 4546050 (1985-10-01), Amberger et al.
patent: 4570328 (1986-02-01), Price et al.
patent: 4690871 (1987-09-01), Gordon
K. Hoshino et al. "Copper Interconnects for ULSI Applications".
Donald Gardner et al. "Encapsulated Copper Interconnection Devices Using Sidewall Barriers", Jun. 11-12, 1991 VMIC Conference.

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