Process for fabricating complementary field effect transistors h

Details Process for fabricating complementary field effect transistors h Process for fabricating complementary field effect transistors h

1994-07-08

1996-05-28

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 44, 437 34, 437 57, H01L 21336

Patent

active

055211062

ABSTRACT:
A process for fabricating a semiconductor device comprising the steps of forming a gate insulation layer on a first conductive type semiconductor substrate, forming a polycrystalline silicon layer on the gate insulation layer, and selectively removing the polycrystalline silicon layer to form a gate electrode and a direct contact electrode. The process also includes a step of forming a photoresist mask masking the direct contact electrode at least at the side opposing the gate electrode, and performing ion implantation of a second conductive type impurity for forming an impurity diffused layer at both sides of the gate electrode. The direct contact electrode and the impurity diffused layer are electrically connected by a conductive layer covering the surface of one of the impurity diffused layer and the side surface of the direct contact electrode.

REFERENCES:
patent: 4374700 (1983-02-01), Scott et al.
patent: 4547959 (1985-10-01), Rusch et al.
patent: 4792835 (1988-12-01), Sacarisen et al.
I. Sakai et al., "A New Salicide Process (PASET) for Sub-half Micron CMOS", 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 66-67.
T. Tang et al., "VLSI Local Interconnect Level Using Titanium Nitride", IEDM 1985, pp. 590-593.

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