Process for fabricating an integrated circuit using local silici

Details Process for fabricating an integrated circuit using local silici Process for fabricating an integrated circuit using local silici

1991-02-26

1993-02-16

Quach, T. N.

Fishing, trapping, and vermin destroying

437 41, 437 47, 437 60, 437193, 148DIG19, H01L 21283, H01L 21336

Patent

active

051871220

ABSTRACT:
A process for fabricating a semiconductor device using local silicide interconnection lines make it possible to fabricate an integrated circuit having a plurality of electronic elements disposed on a semi-conductor substrate. The electronic elements are formed on the substrate such that they are grouped into a first region and a second region adjacent to the first region, each of these regions having predetermined conductivities. The first region has a layer of dielectric material disposed upon it with at least one capacitive element disposed on the dielectric layer. The capacitive element includes a first electrode layer and a second electrode layer. The second region has at least one double junction metal-insulator semi-conductor field effect transistor (MISFET) located therein. The MISFET includes at least three regions, a gate region and two active regions, a source region and a drain region. In accordance with the teachings of the present invention, a process is provided whereby one of said two active regions is electrically connected by a first local connection line to the first electrode layer of the capacitive element, a bond pad is disposed on the gate region, a source bond pad is disposed on the source region, a drain bond pad is disposed upon a drain region and a second electrode layer of the capacitive element, simultaneously, in the same formation step. This is advantageously accomplished inter alia by depositing and then etching the silicide of a refractory metal.

REFERENCES:
patent: 4994402 (1991-02-01), Chiu
patent: 5013678 (1991-05-01), Winnerl et al.
patent: 5026657 (1991-06-01), Lee et al.
"TiSi.sub.2 strap formation by Ti-amorphous-Si reaction" J. Vac. Sci. Technol. B 6 (6), Nov./Dec. 1988 pp. 1734-1739, H. J. W. van Houtum et al.
"Kinetics aspects of TiSi.sub.2 deposition without silicon consumption" Appl. Phys. Lett. 55 (15) Oct. 9, 1989 pp. 1549-1551, D. Bensahel, et al.
"Development of the Self-Aligned Titanium Silicide Process for VLSI Application" IEEE Journal of Solid-State Circuits Vo.. SC-20 No. 1 Feb., 1985 pp. 61-69, M. E. Alperin et al.

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