Process for fabricating an integrated circuit

Details Process for fabricating an integrated circuit Process for fabricating an integrated circuit

1989-04-14

1990-09-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 28, 437 29, 437 32, 437 45, 437 59, 437917, 148DIG9, 148DIG10, H01L 21265

Patent

active

049563050

ABSTRACT:
The invention relates to a pnp lateral transistor comprised of two regions of p-type conductivity which are incorporated into the surface of a semiconductor area of n-type conductivity and constitute the emitter and collector regions. The portion of the semiconductor area of n-type conductivity located between these two regions constitutes the active base region. The invention is based on the fact that the active base region includes below the semiconductor surface and adjacent to the emitter region and to the collector region; a buried semiconductor region containing additionally counter-doping impurities relative to the remaining surrounding base region area, which buried region produces a conductive channel for the minority charge carriers in the base region. This substantially reduces the parasitic surface recombination and substrate transistor influences, and achieves a very high direct current gain in the lateral transistor.

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patent: 4637125 (1987-01-01), Iwasaki et al.
patent: 4649629 (1987-03-01), Miller et al.
M. R. MacPherson, "The Adjustment of MOS Transistor Threshold Voltage by Ion Implantation", Appl. Phys. Lett., vol. 18, No. 11, 6/71, pp. 502-504.
Fischer, "Electron Mobility in Si-MOSFETS with an Additional Implanted Channel", Solid State Electronics, 1979, vol. 22, pp. 225-228.
Sigmon, "MOS Threshold Shifting by Ion Implantation", Solid State Electronics, 1973, vol. 16, pp. 1217-1232.

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