Process for fabricating an EPROM cell array organized in a table

Details Process for fabricating an EPROM cell array organized in a table Process for fabricating an EPROM cell array organized in a table

1990-04-06

1992-01-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 49, 437196, 437968, H01L 2336, H01L 21265

Patent

active

050810561

ABSTRACT:
A process for fabricating an integrated memory matrix of EPROM cells having a "tablecloth" organization, with source and drain lines parallel among each other and running between parallel strips of isolating field oxide, floating gate structures formed between said source and drain lines and control gate lines running parallel among each other and perpendicularly to said source and drain lines and over said floating gate structures, utilizes a mask through which a stack, formed by a second level polysilicon layer, an interpoly isolating dielectric layer, a first level polysilicon layer and a gate oxide layer, is etched for defining in a longitudinal sense the gate structures (i.e. the channel length) of the EPROM cells. The gate structures are subsequently defined in a transversal sense by etching through another mask a stack comprising a third level polysilicon layer deposited directly over said second level polysilicon layer, said interpoly dielectric layer and said first level polysilicon layer. Said other mask also defines control gate lines running perpendicularly to said parallel drain, source and field oxide lines.

REFERENCES:
patent: 4377818 (1983-03-01), Kuo et al.
patent: 4780424 (1988-10-01), Holler et al.
patent: 4792925 (1988-12-01), Corda et al.
patent: 4935378 (1990-06-01), Mori
patent: 5005060 (1991-04-01), Mazzali

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