Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including diode
Reexamination Certificate
2000-06-05
2003-04-29
Smith, Matthew S. (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including diode
C438S048000, C438S022000, C438S023000, C438S024000, C438S979000, C438S983000, C257S021000, C257S082000, C257S084000, C257S104000, C257S105000, C257S106000
Reexamination Certificate
active
06555440
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to semiconductor devices and more particularly to methods of fabricating diode devices, including PIN diodes.
BACKGROUND ART
There are a number of alternative architectures for forming diode devices. Typically, contacts for a P-doped region and an N-doped region are on a single side of a semiconductor substrate in which the PN junction is formed. The two regions are formed in separate diffusion steps that implant dopants from the same substrate side.
Another available architecture is one in which the P-doped and N-doped regions are on opposite sides of a substrate. This architecture is particularly suitable for fabricating PIN diodes, since these diodes require an intermediate intrinsic region. PIN diodes may be used as RF (radio frequency) attenuators and switches. When a forward bias is applied to the diode, holes and electrons are created and then combined in the intrinsic region, so that forward conduction can occur. Removing the forward bias does not immediately cease conduction of current, since the charge carriers require some time to recombine. As a result, a high frequency signal may be superimposed on the forward bias current. The PIN diode then functions as a current controlled resistor that presents a linear resistance to the flow of RF current through the diode. At high frequencies, the resistance decreases the forward bias current increases. If the current is used to switch the PIN diode, the diode can be used for phase shifting or pulse modulation.
The series resistance (Rs) of the PIN diode is generally insensitive to the junction areas of the intrinsic region with the P-doped and N-doped regions, but is very sensitive to the thickness of the intrinsic region between the two junction areas. Rs varies roughly as the square of the intrinsic region distance. One known method for controlling the distance between the junctions is to isotropically form a pit in the back side of the substrate
10
, as shown in FIG.
1
. While the drawing is not shown to scale, the thickness of the substrate
10
may be 76.8 microns, while the depth of the bottom side pit may be 45.2 &mgr;m. An acceptable effective thickness (W) between a top P-diffusion region
12
and a bottom N-diffusion region
14
is 14.7 microns, with the thickness of the top diffusion region being 4.3 microns, and the thickness of the bottom diffusion region being 12.6 microns. The PIN diode
16
of
FIG. 1
also includes a bottom side metallization
18
, which may be a combination of a nickel/gold alloy and a gold plating. A channel stop
20
is formed by providing a ring diffusion of a dopant, such as phosphorous, to provide an N-type channel stop. The channel stop forms a reverse junction at the surface of the substrate
10
to inhibit leakage of current flow as a result of surface inversion. The top P-diffusion region
12
may be formed by introducing boron into the substrate, while the bottom N-diffusion region may be formed by introducing phosphorous.
The PIN diode
16
also includes a patterned oxide layer
22
and a patterned nitride layer
24
. Openings are formed through these layers
22
and
24
to expose a portion of the top P-diffusion region
12
. A gold button
26
is deposited within the exposed area in order to provide an ohmic contact with the top P-diffusion region. Typically, there is a metallization that is deposited prior to the gold button. For example, a first layer of titanium and a second layer of platinum may be formed prior to the gold button.
One concern with the prior art process relates to the alignment of the bottom side pit
28
with the top side junction. A specially designed infrared mask aligner has been used, but the aligner is relatively ineffective if the intrinsic region has a thickness (W) greater than 100 microns. Moreover, the etching of the pits
28
is sometimes problematic, since it requires wax mounting of the wafer and spot etching in order to achieve uniformity. Utilizing wafers having a thickness of greater than 177.8 microns is not a consideration. Because of the breakage concerns that result from using relatively thin substrates, silicon wafers having a diameter of approximately 50.8 millimeters are typically used. As a result, the cost savings that are associated with economies of scale are limited.
Another diode device architecture is described in U.S. Pat. No. 5,268,310 to Goodrich et al. The architecture provides a mesa-type PIN diode which preferably takes the shape of a truncated frustum of a cone. The fabrication of the PIN diode includes providing a substrate having an N-type conductivity. An intrinsic semiconductor layer (preferably silicon) is epitaxially formed on the top surface of the substrate. Within a top region of the epitaxial intrinsic layer, boron is implanted in order to provide the P-type junction. The side walls of the mesa-shaped intrinsic semiconductor layer are doped with phosphorous in order to provide an N-type region. While the structure operates well for its intended purpose, the fabrication process can be costly.
What is needed is a method of fabricating a diode device that provides a level of scalability which accommodates fabrication cost efficiency. What is further needed is a PIN diode device that is formed by such a method.
SUMMARY OF THE INVENTION
A method of fabricating a diode device in a <100> crystal oriented silicon substrate having a top surface and a bottom surface includes forming top and bottom regions of opposite conductivity types and anisotropically etching into the top surface to form an inverted pyramidal pit that terminates prior to reaching the bottom surface. In the preferred embodiment, the diode device is a PIN diode that is formed simultaneously with an array of PIN diodes in an unconventionally large semiconductor wafer. For example, the wafer may have a thickness of at least 250 microns and a diameter of 101.6 millimeters.
In a first step, an oxide layer is formed on the top surface of the wafer. For example, a silicon dioxide may be thermally grown and then photolithographically patterned to provide a channel stop mask for a subsequent diffusion step. Typically, the thermally grown oxide is simultaneously formed on the bottom side of the wafer, but is removed with the selected portions on the top side. The wafer is then phosphorous diffused in the exposed channel stop and along the bottom side of the wafer. This forms the N-junction at the bottom surface and forms the channel stop which inhibits current leakage that might otherwise result from surface inversion.
In the next step, a thermal oxide is grown to cover the channel stop diffusion and to cover the bottom side of the wafer. The functions of the oxide are to reduce stress on the channel stop diffusion and to provide an etch stop for a subsequent bottom side nitride etch.
A nitride layer (typically silicon nitride) is deposited at both the top side and the bottom side of the wafer. Conventional low pressure chemical vapor deposition (LPCVD) processing may be used. A pit etch mask can then be formed from the thermal oxide and the nitride layers in order to expose a square area in which the pit is to be etched. The nitride is dry etched using a conventional dry etch process. The thermal oxide on the top side is wet etched in order to define the area for the pit. While the array of pits formed in a large wafer may have a constant pitch, the creation of pits should terminate approximately 3.175 millimeters from the edge of the wafer, in order to reduce the susceptibility of the wafer to breakage. Edge formation of pits may be prevented by providing the proper design of the pit etch mask or by subsequently coating the outer edge of the wafer with photoresist.
The exposed silicon within a square perimeter of the pit etch mask is anisotropically etched in KOH or other anisotropic etchant to form the pit. The nitride on the bottom side of the wafer protects the bottom side from being etched. If the etching is allowed to continue until it reaches an apex in the inverted pyramid, etching will effectiv
Agilent Technologie,s Inc.
Lee, Jr. Granvill D.
Smith Matthew S.
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