Process for fabricating a semiconductor package and...

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Reexamination Certificate

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C257S676000, C257S677000

Reexamination Certificate

active

10827612

ABSTRACT:
A semiconductor package includes a flat metal leadframe including spaced apart portions, at least some of which constitute electrical connection leads. A filling material fills the spaces that separate the spaced apart portions of the leadframe to form a plate before fastening an integrated circuit chip to the front of the leadframe. Electrical connections are made between the chip and the electrical connection leads. The chip is then encapsulated on the front of the leadframe using a formed or attached encapsulant.

REFERENCES:
patent: 5821532 (1998-10-01), Beaman et al.
patent: 6268654 (2001-07-01), Glenn et al.
patent: 6545332 (2003-04-01), Huang
patent: 6737736 (2004-05-01), Abe et al.
patent: 6869813 (2005-03-01), Okazaki
patent: 2002/0093026 (2002-07-01), Huang
patent: 2003/0075792 (2003-04-01), Ruhland
patent: 05 291546 (1993-11-01), None
patent: 05 343655 (1993-12-01), None
patent: 06 349870 (1994-12-01), None
patent: 09 102580 (1997-04-01), None
Preliminary French Search Report, FR 03 05263, dated Jan. 21, 2004.

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