Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-06-18
2001-04-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S433000, C438S300000, C257S332000, C257S337000, C257S390000
Reexamination Certificate
active
06218265
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor non-volatile memory device, obtained by means of a Shallow Trench Isolation (STI) technique, adapted to guarantee the electrical continuity of the self-aligned source formed by means of a SAS (Self-Aligned Source) process.
2. Discussion of the Related Art
The main features of the STI technology are the elimination of the lateral field oxide (bird's beak), the use of a deposed oxide instead of a thermal oxide, and an excellent oxide planarization over the entire silicon wafer surface. This results in a high scalability of the STI process and makes it suitable, for example, for use in high density Flash memories.
FIGS. 1-3
show some of the main steps of the STI process:
FIG. 1
shows the cross-section of a silicon layer after a vertical etching, made using an oxide
1
and nitride
2
mask, in order to form trenches which separate the future silicon active areas
3
from the isolation or field oxide regions
5
. Afterwards, a sidewall oxidation at high temperature is used to passivate the etched surface, while obtaining a weak oxide thinning at the corner of the active area (not shown in the Figures).
FIG. 2
shows the same cross-sectional view of
FIG. 1
, after the step of filling the trenches with oxide
4
, a possible selective etching using a counter-mask to reduce the difference in oxide thickness between the active areas
3
and the isolation areas
5
, and the subsequent chemical mechanical polishing step which stops on the nitride layer
2
and it provides an excellent planarization of the filling oxide
4
all over the silicon wafer surface.
Finally
FIG. 3
shows the same cross section of the device after the removal of the nitride mask
2
by means of a suitable chemical etching.
FIG. 4
shows a top-plan view of a portion of a semiconductor memory device matrix, at an intermediate fabrication step: in particular, after active areas
3
are defined that form parallel lines alternated with isolation regions
5
according to the previously described process (FIGS.
1
-
3
), continuous lines
7
are defined on a first polysilicon layer along the active areas (FIG.
5
), by means of deposition and subsequent selective etching. Then an intermediate dielectric layer
9
(for example ONO) is formed over the entire surface and at last other parallel lines
6
, defined in a second polysilicon layer and transverse to the active areas
3
, are formed by means of deposition and selective etching, these lines
6
corresponding to the future word lines (FIG.
6
).
FIG. 5
shows a cross sectional view taken along line V—V of
FIG. 4
, after 2nd poly layer definition and before intermediate dielectric and 1st polysilicon layer definition, that is the cross-section of a matrix's common source line for those memory cells belonging to two contiguous word lines
6
.
FIG. 5
, for clarity, does not show the intermediate dielectric layer
9
.
FIG. 6
shows a cross-sectional view taken along line VI—VI of an active area's line
3
of FIG.
4
.
FIG. 7
, similarly to
FIG. 5
, shows a cross-sectional view of a common source line at the process final step, that is after the source and drain implantation. The electrical continuity of the self-aligned source with STI process, and more in general with completely recessed isolations of the silicon, is a problem due to the different silicon level along the common source line between active areas (high zones) and isolation areas (low zones). In fact, along the common source lines there are differences of level usually of about half a micron, with a submicrometric periodicity (for example 0.7-0.8 &mgr;m).
The implantation technology alone is not able to guarantee a perfect connection between the high zones (active areas
3
) and the low zones (isolation areas
5
) of the silicon, as shown in FIG.
7
. Moreover, the use of the titanium salicide along the common source line in order to reduce its resistivity, is not practical without a perfect accordance of the doping depth with the silicon trench walls, in order to avoid the complete consumption of the junction from the salicidation process and the subsequent short-circuit with the substrate.
In view of the state of the art described, it is an object of the present invention to provide a technological process which is able to guarantee the electrical continuity along the common source lines of the matrix of memory cells, even using the STI technique.
SUMMARY OF THE INVENTION
According to the present invention, this and other objects are achieved by a process for fabricating a semiconductor non-volatile memory device arranged in rows and columns in a matrix structure, comprising a first step of forming active area's parallel lines delimited by field oxide lines by means of a Shallow Trench Isolation process, a second step of forming matrix rows which extend transverse to the active area lines, a third step of forming common source lines alternated between pairs of matrix rows, said second step comprising a first sub-step of forming first lines in a first polysilicon layer, along the active area lines, a second sub-step of forming an intermediate dielectric layer, a third sub-step of forming second lines in a second polysilicon layer for defining the matrix rows, a fourth sub-step of defining the intermediate dielectric layer, a fifth sub-step of etching the first polysilicon lines, wherein the first polysilicon lines have interruptions in regions of the active area lines corresponding to the future common source lines of the matrix, so that, during the fifth etching sub-step, simultaneously with the first polysilicon lines etching, the regions of the active area lines not covered with the first polysilicon lines are etched in order to reduce the difference of level along the common source lines between the regions of the active area lines and the regions of the field oxide lines and consequently to guarantee the electrical continuity of the common source regions of the memory device.
REFERENCES:
patent: 3988619 (1976-10-01), Malaviya et al.
patent: 4258466 (1981-03-01), Kuo et al.
patent: 4905062 (1990-02-01), Esquivel et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5025494 (1991-06-01), Gill et al.
patent: 5103274 (1992-04-01), Tang et al.
patent: 5453637 (1995-09-01), Fong-Chun et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5578519 (1996-11-01), Cho
patent: 5679599 (1997-10-01), Mehta
patent: 5696019 (1997-12-01), Chang
patent: 5698879 (1997-12-01), Aritome et al.
patent: 5753561 (1998-05-01), Lee et al.
patent: 5760436 (1998-06-01), Chung
patent: 5874346 (1999-02-01), Fulford, Jr. et al.
patent: 5915195 (1999-06-01), Fulford, Jr. et al.
patent: 5990527 (1999-11-01), Wen
patent: 6001706 (1999-12-01), Tan et al.
patent: 6060739 (2000-05-01), Saitoh
European Search Report from European Patent Application 98830388.9, filed Jun. 30, 1998.
Galanthay Theodore E.
Malsawma Lex H.
Morris James H.
Smith Matthew
STMicroelectronics S.r.l.
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