Process for fabricating a semiconductor memory cell having thin-

Details Process for fabricating a semiconductor memory cell having thin- Process for fabricating a semiconductor memory cell having thin-

1992-09-03

1994-09-20

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 40, 437101, 437193, H01L 2170, H01L 2700

Patent

active

053489039

ABSTRACT:
A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).

REFERENCES:
patent: 5034797 (1991-07-01), Yamanaka et al.
patent: 5145799 (1992-09-01), Rodder
patent: 5173754 (1992-12-01), Manning
H. Kuriyama, et al., "An Asymmetric Memory Cell Using a C-TFT for ULSI SRAMs", 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39, 1992.
K. Itabashi, et al., "A Split Wordline Cell For 16Mb SRAM Using Polysilicon Sidewall Contacts", IEEE Proc. Int. Electron Dev. Meeting, pp. 477-480, Dec. 1991, Washington D.C.
H. Ohkubo, et al., "16Mbit SRAM Cell Technologies for 2.0V Operation", IEEE Proc. Int. Electron Dev. Meeting, pp. 481-484 Dec. 1991, Washington D.C.

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