Process for fabricating a semiconductor integrated circuit utili

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

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438717, 438735, 438738, 438782, H01L 21302

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active

061627364

ABSTRACT:
In a method of manufacturing a semiconductor device, a plurality of inter layer conductive path is formed through a first resist pattern which in turn is formed by an exposure of a hole pattern mask. A plurality of conductive lines is formed, adjacent to the layer of the conductive paths, through a second resist pattern which in turn is formed by double exposure of a line pattern mask and the hole pattern mask. Each conductive line is positioned on at least one of the conductive paths. Or alternatively, each conductive path is positioned between the lines.

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patent: 5882827 (1999-03-01), Nakao
patent: 6043164 (2000-03-01), Nguyen et al.
Hisashi Watanabe "2.times.2 Phase Mask For Arbitrary Pattern Formation" Jpn. J. Appl. Phys. vol. 33 (1994) pp. 6790-6795 Part 1, No. 12B, Dec. 1994.

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