Process for fabricating a semiconductor device having contact ho

Details Process for fabricating a semiconductor device having contact ho Process for fabricating a semiconductor device having contact ho

1997-01-22

1999-10-26

Quach, T. N.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438353, 438637, 438645, 438648, 438655, H01L 2128

Patent

active

059727748

ABSTRACT:
A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a silicon substrate, and a contact hole is formed in an inter-level insulating layer of silicon oxide exposing a part of the upper silicon nitride layer and a part of the titanium silicide layer into the contact hole; while the inter-level insulating layer is being selectively etched so as to form the contact hole, the upper silicon nitride layer serves as an etching stopper, and the contact hole never reaches the silicon substrate beneath the buried isolating structure.

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