Process for fabricating a self aligned interconnect structure in

Details Process for fabricating a self aligned interconnect structure in Process for fabricating a self aligned interconnect structure in

1993-03-03

1994-11-01

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437189, 437193, 437200, 437915, H01L 2170, H01L 2700

Patent

active

053607570

ABSTRACT:
A process for fabricating stacked gate structures (10, 11) and local interconnects (50, 52), in which portions (32, 34) of the thin-film channel layers (20, 22) are exposed by etching away portions of overlying insulating layers (28, 30). A masking layer (40) is formed to overlie the thin-film channel layers (20, 22) and the insulation layers (28, 30), and openings (42, 44) are formed in the insulation layer (40). The openings (42, 44) expose the exposed portions (32, 34) of the thin-film layers (20, 22) and portions (46, 48) of the substrate (12). Interconnects pads (50, 52) are formed to overlie the masking layer (40) and electrically contact the exposed portions of the thinfilm layers (20, 22) and the exposed portions (46,48) of the substrate (12). In regions where the insulation layers (28, 30) have not been removed, an interconnect pad (52) electrically contacts only a portion (48) of the substrate (12 ). In regions where insulation layers (28, 30) are removed, an interconnect pad (50) electrically contacts both the thin-film channel layer (22) and a portion (46) of the substrate (12).

REFERENCES:
patent: 4994873 (1991-02-01), Madan
patent: 5173450 (1992-12-01), Wei
patent: 5187122 (1993-02-01), Bouis
patent: 5212399 (1993-05-01), Manning
patent: 5215932 (1993-06-01), Manning

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