Process for fabricating a MOSFET device having reduced reverse s

Details Process for fabricating a MOSFET device having reduced reverse s Process for fabricating a MOSFET device having reduced reverse s

1995-06-02

1996-09-03

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437241, 437240, H01L 21265, H01L 2102

Patent

active

055523323

ABSTRACT:
A process for the fabrication of an MOSFET device includes the formation of a buffer layer (28) overlying the surface of a semiconductor substrate (14) adjacent to a gate electrode (18). A defect compensating species is diffused through the buffer layer (28) and through a gate dielectric layer (12) to form a defect-compensating region (30) at the surface (14) of the semiconductor substrate (10). The defect-compensating region (30) in conjunction with the buffer layer (28) minimize and control the population of point defects in the channel region (22) of the semiconductor substrate (10). By controlling the population of point defects in the channel region (22), a substantially uniform doping profile is maintained in a shallow doped region (16) formed in the semiconductor substrate (10) at the substrate surface (14). The maintenance of a uniform doping profile in the shallow doped region (16) results in improved threshold voltage stability as the lateral dimension of the channel region (22) is reduced.

REFERENCES:
patent: 5397720 (1995-03-01), Kwong et al.
patent: 5407870 (1995-04-01), Okada et al.
patent: 5460992 (1995-10-01), Hasegawa
Paul G. Y. Tsui et al., "Suppression of MOSFET Reverse Short Channel Effect by N20 Gate Poly Reoxidation Process", 1994 IEDM San Francisco, California, Dec. 11-14, pp. 501-504.
S. Kusunold et al., "Hot-Carrier-Resistant Structure by Re-oxidized Nitrided Oxide Sidewall for Highly Reliable and High Performance LDD MOSFETS", 1991 IEEE, pp. 25.4.1-25.4.4.

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