Process for fabricating a low breakdown voltage device for polys

Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal

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29571, 29577R, 29578, 29580, 148174, 148175, 156647, 156653, 156657, 156662, 357 13, 357 20, 357 23, 357 41, 357 55, 357 59, 357 60, H01L 2122, H01L 21302, H01L 2978

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041027140

ABSTRACT:
A structure and process are disclosed for making a low-voltage breakdown p-n junction in a semiconductor substrate. The process comprises the step of etching a V-shaped groove in a semiconductor substrate of a first conductivity type, with an anistropic etchant, followed by depositing a layer of epitaxial semiconductor material of a second conductivity type in the V-shaped groove. There results a p-n junction with a small radius of curvature at the apex of the V-shaped groove having a correspondingly low breakdown voltage.

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Declercq; M. J., "New C-MOS . . . , Anisotropic Etching of Silicon" IEEE J. Solid-State Circuits, vol. SC-10, No. 4, Aug. 1975, pp. 191-197.
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