Process for fabricating a high-speed CMOS TTL semiconductor devi

Details Process for fabricating a high-speed CMOS TTL semiconductor devi Process for fabricating a high-speed CMOS TTL semiconductor devi

1988-12-30

1990-04-24

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 56, 437195, 357 2311, 357 42, H01L 21265

Patent

active

049200666

ABSTRACT:
A process for fabricating a high-speed CMOS TTL semiconductor device, wherein the operational speed of a semiconductor device is controlled by adjusting the capacitance of its field region. The capacitance of the field region is adjusted by the thickness thereof, which is determined by the control of diffusion heating cycles in the fabrication sequence according to the invention.

REFERENCES:
patent: 4152823 (1979-05-01), Hall
Black et al., "CMOS Process for High-Performance Analog LSI", International Electron Devices Meeting, Dec. 6-8, 1976, pp. 331-334.
May et al., "High-Speed Static Programmable Logic Array in LOCMOS", IEEE Journal of Solid State Circuits, vol. SC-11, No. 3, 6/1976, pp. 365-368.

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