Process for fabricating a heterostructure-channel...

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor

Reexamination Certificate

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C257S183000

Reexamination Certificate

active

07436005

ABSTRACT:
The insulated-gate field-effect transistor includes a substrate surmounted by a layer of silicon-germanium alloy, the ratio of the germanium concentration to the silicon concentration of which increases towards the surface of the substrate. The transistor is formed on the active zone in the silicon-germanium alloy layer and lies between two isolating zones. The transistor includes a narrow heterostructure strained-semiconductor channel including a SiGe alloy layer in compression and a silicon layer in tension, extending between the gate and a dielectric block buried in the substrate.

REFERENCES:
patent: 6555839 (2003-04-01), Fitzgerald
patent: 6989570 (2006-01-01), Skotnicki et al.
patent: 2002/0089003 (2002-07-01), Lee
patent: 2 838 237 (2003-10-01), None
Tezuka et al.; “Novel Fully-Depleted SiGe-on-Insulator pMOSFETs with High-Mobility SiGe Surface Channels”, IEDM Technical Digest, Washington DC, Dec. 2-5, 2001, pp. 3361-3363, XP010575278.
Lee et al., “Performance Enhancement on Sub-70nm Strained Silicon SOI MOSFETs on Ultra-thin Thermally Mixed Strained Silicon/SiGe on Insulator (TM-SGOI) Substrate with Raised S/D”; IEDM Technical Digest, San Francisco, CA, Dec. 8-11, 2002, New York, NY, pp. 946-948; XP010626195.
Skotnicki, “Silicon on Nothing(SON)—Fabrication, Material and Devices”; Electrochemical Society Proceedings, New Jersey, US; vol. 2001, No. 3 dated Mar. 25, 2001, pp. 391-402; XP008014133.
Yee-Chia et al., “Enhanced Performance in Sub-100nm CMOSFETs Using Strained Epitaxial Silicon-Germanium”, Electron Devices Meeting, Dec. 10-13, 2000, Piscataway, New Jersey, USA; pp. 753-756; XP010531871.

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