Fishing – trapping – and vermin destroying
Patent
1995-02-28
1997-02-25
Niebling, John
Fishing, trapping, and vermin destroying
437 44, 257345, H01L 218234
Patent
active
056058551
ABSTRACT:
A process for fabricating a graded-channel MOS device includes the formation of a masking layer (16) on the surface of a semiconductor substrate (10) and separated from the surface by a gate oxide layer (12). A first doped region (22) is formed in a channel region (20) of the semiconductor substrate (10) using the masking layer (16) as a doping mask. A second doped region (24) is formed in the channel region (20) and extends from the principal surface (14) of the semiconductor substrate (10) to the first doped region (22). A gate electrode (34) is formed within an opening (18) in the masking layer (16) and aligned to the channel region (20). Upon removal of the masking layer (16) source and drain regions (36, 38) are formed in the semiconductor substrate (10) and aligned to the gate electrode (34).
REFERENCES:
patent: 4371955 (1983-02-01), Sasaki
patent: 4599118 (1986-07-01), Han et al.
patent: 4680604 (1987-07-01), Nakagawa et al.
patent: 4697198 (1987-09-01), Komori et al.
patent: 5021845 (1991-06-01), Hashimoto
patent: 5082794 (1992-01-01), Pfiester et al.
patent: 5175119 (1992-12-01), Matsutani
patent: 5372960 (1994-12-01), Davies et al.
patent: 5374574 (1994-12-01), Kwon
patent: 5374575 (1994-12-01), Kim et al.
patent: 5399508 (1995-03-01), Nowak
patent: 5427964 (1995-06-01), Kaneshiro et al.
patent: 5429956 (1995-07-01), Shell et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5472897 (1995-12-01), Hsu et al.
patent: 5482878 (1996-01-01), Burger et al.
patent: 5484743 (1996-01-01), Ko et al.
patent: 5538913 (1996-07-01), Hong
Yoshinori Okumura, "Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability", IEEE Transactions on Electron Devices, vol. 39, No. 11, Nov. 1992, pp. 2541-2552.
Chang Ko-Min
Luo Shiang-Chyong
Orlowski Marius
Sun Shih-Wei
Swift Craig
Booth Richard A.
Dockrey Jasper W.
Meyer George R.
Motorola Inc.
Niebling John
LandOfFree
Process for fabricating a graded-channel MOS device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for fabricating a graded-channel MOS device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating a graded-channel MOS device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1973826