Process for fabricating a flash EPROM having reduced cell size

Details Process for fabricating a flash EPROM having reduced cell size Process for fabricating a flash EPROM having reduced cell size

1991-12-12

1993-05-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG19, 148DIG50, H01L 21266

Patent

active

052100472

ABSTRACT:
A process for fabricating an electrically programmable read-only memory array having increased density includes forming recessed field oxide regions in a silicon substrate. Elongated parallel wordline stacks are then formed over the surface of the substrate. Source and drain regions are formed by ion implantation in the openings between these vertical stacks. These openings are then filled with a metal layer until the wafer is substantially planar. This metal layer is then patterned to form drain contact pads and V.sub.SS interconnect strips. The V.sub.SS interconnect strips contact adjacent source regions across field oxide regions that insulate adjacent memory cells.

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patent: 4698787 (1987-10-01), Mukherjee et al.
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patent: 5019527 (1991-05-01), Ohshima et al.
patent: 5110753 (1992-05-01), Gill et al.
"Titanium Disilicide Self-Aligned Source/Drain & Gate Technology," by Lau et al. IEDM, 1982.
"LPCVD Titanium Nitride--Deposition, Properties, and Application to ULSI" by Pintochovski et al., Materials Research Society, 1989.
"Microstructure and Electrical Properties of Titanium Nitride Diffusion Barrier Films Sputtered from a Composite Target," by Wei et al., Materials Research Society, 1989.
"Titanium Nitride Deposition in a Cold Wall CVD Reactor," by A. Sherman, Materials Research Society, 1989.
"A 3.6 mm.sup.2 Memory Cell Structure for 16MB EPROMS," by Hisamune et al., IEDM 1989, pp. 583-586.

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