Semiconductor device manufacturing: process – Having superconductive component
Reexamination Certificate
2001-08-24
2003-04-29
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Having superconductive component
Reexamination Certificate
active
06555393
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits and, more specifically to a transistor having a buried Mott material oxide channel.
2. Description of the Related Art
Silicon based metal oxide semiconductor field effect transistors (MOSFETs) are reaching the limits of scaling (e.g., reduction in size) due to, among other things, doping and double depletion effects. In other words, as semiconductor devices are reduced in size, the depletion regions are placed in closer proximity to one another. This often results in merging or shorting of the adjacent depletion regions.
Silicon MOSFET technology is expected to scale to 0.1 micron channel length devices after the year 2000. Below 0.1 microns however, there are fundamental physical effects which can limit silicon MOSFET technology, including: short channel effects, dopant number fluctuations, ballistic transport and tunneling through thin gate oxides. These effects may limit the minimum channel length in silicon MOSFET technology to an estimated 30 nm.
One solution to the scaling problem is a field effect transistor (FET) formed with a channel oxide capable of undergoing a metal-insulator transition known as a Mott transition (e.g., a Mott FET or MTFET).
A Mott FET is a solid state switching device made entirely of oxide materials and is discussed in more detailed in
Mott Transition Field Effect Transistor,
Newns, et al. Applied Physics Letters, Vol 73, Number 6, pages 780-782, Aug. 10, 1998, incorporated herein by reference. The Mott FET device includes a channel connecting source and drain electrodes, a gate oxide and a gate electrode.
For example, a Mott FET device is shown in FIG.
8
. The device includes a conductive substrate
80
(e.g., Nb-STO (100)-cut crystal) which forms the gate electrode, a gate oxide layer
81
(e.g., strontium titanate (STO)) epitaxially grown on the substrate
80
, a Mott conductor-insulator transition channel
82
(e.g., an epitaxially grown cuprate material such as Y
1−x
Pr
x
Ba
2
Cu
3
O
7−&dgr;
(YPBCO, LCO)), source and drain electrodes
83
and an isolation trench
84
. With the structure shown in
FIG. 8
, when a voltage is applied to the gate
81
, the channel
82
changes from an insulator to a conductor (or vice versa) to make or break a connection between the source and drain
83
.
The Mott FET device is quite distinct from conventional silicon metal oxide field effect transistors in that the channel is a Mott oxide, a material with a characteristic, controllable, metal-insulator transition, rather than a semiconductor. A Mott FET device offers significant potential for scaling to the nanometer dimensions for integration with ferroelectric materials in non-volatile storage roles and for fabrication of multilayer device structures. Mott FET devices remain adequate on a nanoscopic scale which is well beyond the current projected limits of silicon MOSFET scaling.
However, the conventional Mott FET has a number of limitations. Specifically, the structure shown in
FIG. 8
results in the channel layer
82
being exposed to subsequent processing steps, which may damage or undesirably change the channel layer
82
. Further, the epitaxially grown gate oxide
81
provides a somewhat imperfect surface upon which to grow the Mott transition channel layer
82
, which limits the scaling which can be achieved with conventional Mott FETs.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel. The inventive method includes depositing source and drain electrodes onto the substrate, forming a Mott transition channel layer over a substrate, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that electrical contact is made to the Mott transition channel layer) and forming a gate conductor electrode over the insulator layer between the source and drain electrodes.
The inventive method also includes, before the forming of the Mott transition channel layer, cleaning the substrate, wherein the cleaning comprises ultrasound-cleaning using at least one of acetone, isopropanol, and ethanol, in successive stages. After the cleaning, the method includes performing an O
2
ash on the substrate.
The forming of the Mott transition channel layer can include epitaxially forming the Mott transition channel layer and the Mott transition channel layer may comprise a peroskvite oxide layer.
In accumulation type devices, the spacing of the source and drain electrodes defines the channel length. Whereas, in depletion type devices, the channel region is defined by the area under the gate electrode. The method also includes adjusting the conductivity of the channel layer by increasing or decreasing an oxygen content of the channel layer.
The integrated circuit device of the invention includes a Mott transition channel layer over a substrate, an insulator layer over the Mott transition channel layer, source and drain contacts through the insulator layer (to connect to source and drain electrodes that are electrically connected to the Mott transition channel layer) and a gate conductor electrode over the insulator layer between the source and drain electrodes.
The Mott transition channel layer may be an epitaxially formed Mott transition channel layer, including a peroskvite oxide layer. The spacing of the source and drain electrodes is defined by the gate channel length in accumulation devices and by the gate electrode length in depletion devices. The conductivity of the channel layer is adjusted by increasing or decreasing an oxygen content of the channel layer.
With the invention, the Mott transition channel layer is buried below the gate oxide layer which protects the channel layer from damage or change during subsequent processing. Also, the invention forms the channel layer on a clean substrate using an epitaxial growth process, which provides superior long-range order quality and fewer imperfections when compared to conventional structures. Additionally, the length of the channel region is easily controlled with the invention during the patterning of the conductive contacts.
REFERENCES:
patent: 5401714 (1995-03-01), Chaudhari et al.
patent: 5536584 (1996-07-01), Sotokawa et al.
patent: 5571737 (1996-11-01), Sheu et al.
patent: 5608231 (1997-03-01), Ugajin et al.
patent: 5652156 (1997-07-01), Liao et al.
patent: 6121642 (2000-09-01), Newns
patent: 6259114 (2001-07-01), Misewich et al.
patent: 3-079081 (1991-04-01), None
patent: 5-102543 (1993-04-01), None
patent: 5-190924 (1993-07-01), None
patent: 6-338637 (1994-12-01), None
patent: 6-342172 (1994-12-01), None
patent: 07094739 (1995-04-01), None
patent: 08274195 (1996-10-01), None
patent: 9-312424 (1997-12-01), None
patent: 1056177 (1998-02-01), None
patent: 2000294796 (2000-10-01), None
patent: 2000332133 (2000-11-01), None
Newns et al., “Mott Transition Field Effect Transistor”, vol. 73, No. 6, Aug. 10, 1998, p. 780-782.
Misewich James A.
Schrott Alejandro G.
Scott Bruce A.
Lattin Christopher
McGinn & Gibb PLLC
Niebling John F.
Underweiser, Esq. Marian
LandOfFree
Process for fabricating a field-effect transistor with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for fabricating a field-effect transistor with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating a field-effect transistor with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3031296