Process for fabricating a control gate for a floating gate FET

Details Process for fabricating a control gate for a floating gate FET Process for fabricating a control gate for a floating gate FET

1989-11-29

1991-02-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437193, 437200, H01L 21336

Patent

active

049923919

ABSTRACT:
A process of forming a floating gate field-effect transistor having a multi-layer control gate line is disclosed. The multi-layer control gate line includes a first polysilicon layer, a silicide layer provided on the first polysilicon layer, and a second polysilicon layer provided on the silicide layer. The first and second polysilicon layers are formed as undoped polysilicon to improve the adhesion of the polysilicon layers to the silicide layers sandwiched therebetween. After all three layers are formed, the polysilicon layers are doped in an environment including POCl.sub.3. Because the first and second polysilicon layers are formed as undoped layers, all three layers of the control gate line may be formed using a single pump-down.

REFERENCES:
patent: 3881242 (1975-05-01), Nuttall et al.
patent: 4128670 (1978-12-01), Gaensslen
patent: 4373251 (1983-02-01), Wilting
patent: 4389257 (1983-06-01), Geipel, Jr. et al.
patent: 4403394 (1983-09-01), Shepard et al.
patent: 4640844 (1987-02-01), Neppl et al.
patent: 4740479 (1988-04-01), Neppl et al.

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