Process for fabricating a contactless floating gate memory array

Details Process for fabricating a contactless floating gate memory array Process for fabricating a contactless floating gate memory array

1990-04-30

1992-02-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 67, 437200, 148DIG50, H01L 21265, H01L 2176

Patent

active

050875841

ABSTRACT:
A process for fabricating ultra-high density (e.g., 64Mbit) contactless EPROMs and/or flash EPROMs in a silicon substrate is described. Spaced-apart island members are formed of poly 2/ dielectric/poly 1 layers over gate oxide regions. Each island member is associated with one of the cells within the array, and is separated from each other by trenches extending down to either the field oxide or substrate regions. Elongated, parallel, spaced-apart source/drain regions are formed on adjacent sides of the channel regions by ion implantation. The trenches are then filled with an insulating material and a plurality of wordlines patterned across the array. Each wordline makes electrical contact to the control gate members associated with the single row of cells within the array.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee
patent: 4698900 (1987-10-01), Esquivel
patent: 4763177 (1988-08-01), Paterson
patent: 4814286 (1989-03-01), Tam
patent: 4849363 (1989-07-01), Jeuch

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