Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2001-11-01
2003-12-16
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C252S079200, C252S079400, C252S079100, C438S745000, C438S705000, C438S703000, C438S694000
Reexamination Certificate
active
06664197
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT Not Applicable
BACKGROUND OF THE INVENTION
An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor material. Devices that may be formed within the semiconductor material include MOS transistors, bipolar transistors, diodes and diffused resistors. Devices that may be formed within the dielectric include thin-film resistors and capacitors. Typically, more than 100 integrated circuit die (IC chips) are constructed on a single 8 inch diameter silicon wafer. The devices utilized in each dice are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. In current practice, an aluminum alloy and silicon oxide are typically used for, respectively, the conductor and dielectric.
In a similar manner, metallized microelectronic components may be formed on semiconductor wafers or other substrates. Such microelectronic components include, for example, read/write heads, inductive components, capacitors, etc. Unlike the metallized interconnects described above, these microelectronic components include features that directly contribute to the operation of the circuit or device beyond mere interconnection of other components.
Recent technical advances have indicated that it is preferable to form metallized microelectronic components and interconnects from copper rather than the more traditional aluminum. In such microelectronic circuits, the copper is preferably isolated in the desired circuit region through the use of a barrier layer that impedes migration of copper to other areas of the circuit. Copper metallization structures are preferred to the more conventional aluminum structures because the resistivity of copper is significantly lower than that of aluminum.
There are numerous problems relating to the use of copper for these metallized structures that must be overcome before such copper metallized structures are commercially viable. Diffusion of copper is one such problem. Under the influence of an electric field, and at only moderately elevated temperatures, copper moves rapidly through silicon oxide. It is believed that copper also moves rapidly through low-K
e
dielectrics. Such copper diffusion causes failure of devices formed within the silicon.
Another problem is the propensity of copper to oxidize rapidly when immersed in aqueous solutions or when exposed an oxygen-containing atmosphere. Oxidized surfaces of the copper are rendered non-conductive and thereby limit the current carrying capability of a given conductor path when compared to a similarly dimensioned non-oxidized copper path.
A still further problem with using copper in integrated circuits and components is that it is difficult to use copper in a multi-layer, integrated circuit structure with dielectric materials. Using traditional methods of copper deposition, copper generally adheres only weakly to dielectric materials.
The semiconductor industry has addressed some of the foregoing problems in its efforts to make copper interconnects and components commercially viable. With respect to the problems associated with copper diffusion, barrier materials and corresponding structures have been developed to inhibit the diffusion. Such barrier materials include, for example, titanium nitride (TiN), and other refractory metal alloys. The barrier layer is interposed between the substrate and the copper interconnect or component. An adhesion-enhancing layer is often interposed between the barrier layer material and the copper interconnect or component. However, recent advances in electroplating chemistry by Semitool, Inc., have indicated that copper may be directly plated on the barrier layer material. Such advances are disclosed in U.S. Ser. No. 09/045,245, pending, filed Mar. 20, 1998, titled “Apparatus And Method For Electrolytically Depositing Copper On A Semiconductor Workpiece” (Attorney Docket No. SEM4492P0020US), which is hereby incorporated by reference.
Further advances in manufacturing commercially viable copper interconnects and/or components are disclosed in U.S. Ser. No. 09/076,565, pending, filed May 12, 1998, (Attorney Docket No. SEM4492P0051US), titled “Process And Manufacturing Tool Architecture For Use In The Manufacture Of One Or More Protected Metallization Structures On A Workpiece”, which is hereby incorporated by reference. In accordance with the teachings of the foregoing patent application, copper interconnects and/or components are formed on a generally planar workpiece surface. This method of manufacturing such structures is in contrast to the more traditional dual-damascene formation process adopted in the semiconductor industry. In the latter process, the barrier layer material and copper metallization are driven into patterned recesses disposed in the workpiece surface. The deposition of such layers becomes quite difficult as component/interconnect geometries are reduced. Additionally, a processing step known as chemical-mechanical polishing (CMP) must be employed in this latter process. The CMP processing step removes those portions of the deposited barrier and/or metal layers that extend beyond the upper bounds of the patterned recesses. This processing step is often a source of device contamination and mechanical damage to the workpiece. The architecture disclosed in the foregoing patent application may be used to reduce and/or eliminate the need to deposit barrier and copper layers in small recessed geometries and, further, may reduce and/or eliminate the need for executing a CMP processing step in the interconnect/component formation.
In both the traditional dual-damascene process and the more advanced processes disclosed in the '565 application, there is a need to remove thin-film layers, such is the barrier layer and/or copper layer, from the surface of the workpiece. The thin-film layers may need to be removed in a blanket manner from the entire surface of the workpiece, or in a selective manner that leaves a predetermined pattern of the thin-film layers on the workpiece surface.
Removal of the thin-film layer may be problematic. For example, since copper does not form volatile halide compounds, direct plasma etching of copper cannot be employed in fine-line patterning of copper interconnects or components. As such, the present inventors have recognized that alternative processes for removing one or more thin-film layers are now needed if advanced, commercially viable copper interconnects and components are to become a reality. This need which the inventors have now recognize is addressed by the present invention.
BRIEF SUMMARY OF THE INVENTION
A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component is set forth. Generally stated, the process comprises the oxidation of at least a portion of the at least one thin-film layer and the etching of the oxidized thin-film layer using an etchant that selectively etches primarily the oxidized thin-film layer.
Various embodiments of the processes are set forth. In accordance with one embodiment, the oxidizing and etching steps are executed in a generally concurrent manner. Alternatively, the oxidizing and etching steps are executed in a sequential manner and the etching step is executed in a generally non-oxidizing atmosphere.
Specific embodiments of processes are set forth that may be used in the manufacture of copper interconnects structures or devices on a workpiece such as a semiconductor wafer. In such embodiments, the thin-film layer is copper. The etching of the copper may be executed using an etchant comprising sulfuric acid. Likewise, the etching of the copper may be executed using an etchant comprising water, sulfamic acid, and iron (III) chloride. This latter etchant may also comprise further components such as a
Pfeiffer Richard
Stevens E. Henry
Anderson Matthew A.
Christensen O'Connor Johnson & Kindness PLLC
Norton Nadine G.
Semitool Inc.
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