Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-12-11
2001-01-09
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C148S033400, C257S288000, C438S009000, C438S724000, C438S757000, C438S744000
Reexamination Certificate
active
06171973
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
Generally, the invention relates to the etching of the gate material in the fabrication of field-effect transistors.
2. Description of the Related Art
In the fabrication of MOS transistors, polysilicon or an alloy of silicon and germanium is generally used as the gate material. This material is deposited on a thin layer of thermal oxide, also called gate oxide, and then etched to the dimensions of the gate.
The etching, by any means whatsoever, may be carried out using a hard mask which defines the region intended subsequently to form the gate and which protects the said region during the operation. An inorganic material, such as silicon dioxide or silicon nitride, is therefore normally used for the hard mask. The absence of carbon in the material of which the mask is composed, responsible for destroying the gate oxide layer when etching the gate, makes it possible to significantly increase the selectivity of the etching of the gate material made of polycrystalline silicon or of a silicon-germanium alloy with respect to the gate oxide.
Nevertheless, the use of these conventional masks has drawbacks which impair the quality of the transistors fabricated.
It is known to isolate the future active regions of a semiconductor device in a conventional manner (LOCOS) or by shallow trenches (STI or Shallow Trench Isolation) using silicon dioxide. When the hard mask for etching the gate is made of silicon dioxide, its removal runs the risk of cutting away the trenches or of destroying the isolation region because it is of the same nature as the isolation oxide.
Moreover, using a hard mask based on silicon nitride runs the risk of destroying the gate material when removing the mask. This is because the process of etching silicon nitride is very similar to that for silicon, which results in poor etching selectivity between these 2 materials and in detection of the end of etching of the hard mask that occurs at the gate not being sufficient to prevent partial destruction of the gate lying beneath the hard mask.
It would therefore seem to be necessary to develop a process for etching the gate material which does not have the abovementioned drawbacks.
SUMMARY OF THE INVENTION
The inventors have demonstrated that the use of a thin and porous layer based on nitrided silicon oxide SiON, as a hard mask for etching the gate material, makes it possible to overcome the drawbacks observed with the masks of the prior art. The material SiON has all the properties required of a hard mask. Furthermore, its removal is simplified, without in any way destroying either the thermal oxide or the gate material.
In the microelectronics field, nitrided silicon oxide is generally used as material for antireflective layers. In particular, this material limits the reflectivity of tungsten- or aluminium-based subjacent layers during the photolithography of these layers, as well as the parasitic effects of reflection off the subjacent layers during exposure of the photosensitive organic layer.
The invention provides a process for etching the gate material in the fabrication of field-effect transistors, comprising at least the following steps:
a) a thin and porous layer of a SiON-based alloy is deposited on a semiconductor substrate coated with a thermal oxide first layer and with a second layer made of polycrystalline silicon or of a silicon-germanium alloy;
b) the said layer is etched using a resin mask produced on the SiON-based layer, in order to form a hard mask;
c) after the masking resin has been removed, the region predefined by the hard mask in the layer made of polycrystalline silicon or of a silicon-germanium alloy is etched in order to form the future gate; and
d) the SiON-based hard mask is removed.
In step a), “thin layer” should be understood to mean a layer whose thickness is between 500 and 2000 Å, typically 1500 Å. The composition of the alloy of which this layer is composed is preferably Si
x
O
y
N
z
, in which x is between 35 and 45% and z is between 40 and 60%, y making the total up to 100%. These percentages are atomic percentages.
The SiON-based alloy layer may be deposited on the gate material by plasma-enhanced chemical vapour deposition at low temperature, and more particularly at about 300° C.
The etching of the SiON-based hard mask in step b) is advantageously assisted by end-of-etching detection that takes place at the subjacent layer based on polycrystalline silicon or on a silicon-germanium alloy then acting as a stop layer for the operation.
In step c), the etching of the gate in the layer based on polycrystalline silicon or on a silicon-germanium alloy may also be advantageously assisted by end-of-etching detection that takes place at the thermal oxide layer acting as the stop layer for the operation.
In step d), the SiON-based hard mask may be removed chemically, such as especially by liquid etching, or by plasma etching. This operation may advantageously be assisted by end-of-etching detection that occurs as the future gate then acting as a stop layer for the operation.
Alternatively, in step d), the removal of the SiON-based hard mask is preceded by a step of forming lateral spacers based on silicon dioxide or on silicon nitride which are placed on each side of the future gate.
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Gocho et al., “CVD Method of Anti-Reflective Layer Film for Excimer Laser Lithography,” Int. Conf. on Solid State Devices & Materials, Aug. 1993, pp. 570-572.
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Gaillard Fr{acute over (e)}d{acute over (e)}ric
Schiavone Patrick
Conley & Rose & Tayon P.C.
France Telecom
Powell William
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