Process for etching and depositing integrated circuit interconne

Details Process for etching and depositing integrated circuit interconne Process for etching and depositing integrated circuit interconne

1993-07-08

1994-10-11

Kunemund, Robert

Fishing, trapping, and vermin destroying

437195, 437203, 156651, H01L 21283, H01L 2190

Patent

active

053547110

ABSTRACT:
Process for producing an integrated circuit stage formed from a dielectric layer (1) covering interconnection lines (5) and connection points (4), which connect the said lines (5) to conductive parts (6) on the opposite side of the dielectric layer (1). The process consists of forming all the dielectric layer (1) during a single step and then successively etching cavities at the locations of the connection points and the interconnection lines by means of two successively positioned masks and then filling the cavities in a single step with conductive material in order to simultaneously form connection points (4) and interconnection lines (5).

REFERENCES:
IBM Technical Disclosure Bulletin 29 (1986) Aug. No. 3, New York, Integrated Circuit Conductor Line Self-Aligned to Contact Opening.

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