Process for EPROM, flash memory with high coupling ratio

Details Process for EPROM, flash memory with high coupling ratio Process for EPROM, flash memory with high coupling ratio

1994-05-06

1995-07-11

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437191, 437233, 257315, 257316, H01L 21285, H01L 218247

Patent

active

054321123

ABSTRACT:
A semiconductor device is formed on a substrate lightly doped with a dopant, a source region and a drain region in the substrate on the surface thereof, a dielectric layer deposited upon the substrate, a first floating gate layer formed on the dielectric layer, a second floating gate layer formed on the the first floating gate layer, a second dielectric material deposited upon the surface of the first floating gate electrode, a control gate electrode deposited upon the surface of the additional dielectric material, and means for applying a voltage to the control gate electrode.

REFERENCES:
patent: 5089867 (1992-02-01), Lee
patent: 5147813 (1992-09-01), Woo
patent: 5284786 (1994-02-01), Sethi
patent: 5304829 (1994-04-01), Mori et al.

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