Process for EEPROM cell structure and architecture with increase

Details Process for EEPROM cell structure and architecture with increase Process for EEPROM cell structure and architecture with increase

1991-12-23

1994-04-19

Thomas, Tom

Fishing, trapping, and vermin destroying

437 43, 437 48, 437195, 437 97, H01L 2170

Patent

active

053045050

ABSTRACT:
An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

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